Lines Matching refs:RO
1313 class ArithLogicR<string opstr, RegisterOperand RO, bit isComm = 0,
1316 InstSE<(outs RO:$rd), (ins RO:$rs, RO:$rt),
1318 [(set RO:$rd, (OpNode RO:$rs, RO:$rt))], Itin, FrmR, opstr> {
1325 class ArithLogicI<string opstr, Operand Od, RegisterOperand RO,
1329 InstSE<(outs RO:$rt), (ins RO:$rs, Od:$imm16),
1331 [(set RO:$rt, (OpNode RO:$rs, imm_type:$imm16))],
1347 class LogicNOR<string opstr, RegisterOperand RO>:
1348 InstSE<(outs RO:$rd), (ins RO:$rs, RO:$rt),
1350 [(set RO:$rd, (not (or RO:$rs, RO:$rt)))], II_NOR, FrmR, opstr> {
1356 RegisterOperand RO, InstrItinClass itin,
1359 InstSE<(outs RO:$rd), (ins RO:$rt, ImmOpnd:$shamt),
1361 [(set RO:$rd, (OpNode RO:$rt, PF:$shamt))], itin, FrmR, opstr> {
1365 class shift_rotate_reg<string opstr, RegisterOperand RO, InstrItinClass itin,
1367 InstSE<(outs RO:$rd), (ins RO:$rt, GPR32Opnd:$rs),
1369 [(set RO:$rd, (OpNode RO:$rt, GPR32Opnd:$rs))], itin, FrmR,
1373 class LoadUpper<string opstr, RegisterOperand RO, Operand Imm>:
1374 InstSE<(outs RO:$rt), (ins Imm:$imm16), !strconcat(opstr, "\t$rt, $imm16"),
1381 class LoadMemory<string opstr, DAGOperand RO, DAGOperand MO,
1385 InstSE<(outs RO:$rt), (ins MO:$addr), !strconcat(opstr, "\t$rt, $addr"),
1386 [(set RO:$rt, (OpNode Addr:$addr))], Itin, FrmI, opstr> {
1393 class Load<string opstr, DAGOperand RO, SDPatternOperator OpNode = null_frag,
1395 LoadMemory<opstr, RO, mem, OpNode, Itin, Addr>;
1397 class StoreMemory<string opstr, DAGOperand RO, DAGOperand MO,
1400 InstSE<(outs), (ins RO:$rt, MO:$addr), !strconcat(opstr, "\t$rt, $addr"),
1401 [(OpNode RO:$rt, Addr:$addr)], Itin, FrmI, opstr> {
1407 class Store<string opstr, DAGOperand RO, SDPatternOperator OpNode = null_frag,
1410 StoreMemory<opstr, RO, MO, OpNode, Itin, Addr>;
1414 class LoadLeftRight<string opstr, SDNode OpNode, RegisterOperand RO,
1416 InstSE<(outs RO:$rt), (ins mem:$addr, RO:$src),
1418 [(set RO:$rt, (OpNode addr:$addr, RO:$src))], Itin, FrmI> {
1424 class StoreLeftRight<string opstr, SDNode OpNode, RegisterOperand RO,
1426 InstSE<(outs), (ins RO:$rt, mem:$addr), !strconcat(opstr, "\t$rt, $addr"),
1427 [(OpNode RO:$rt, addr:$addr)], Itin, FrmI> {
1470 RegisterOperand RO> :
1471 InstSE<(outs), (ins RO:$rs, RO:$rt, opnd:$offset),
1473 [(brcond (i32 (cond_op RO:$rs, RO:$rt)), bb:$offset)], II_BCC,
1482 class CBranchLikely<string opstr, DAGOperand opnd, RegisterOperand RO> :
1483 InstSE<(outs), (ins RO:$rs, RO:$rt, opnd:$offset),
1493 RegisterOperand RO> :
1494 InstSE<(outs), (ins RO:$rs, opnd:$offset),
1496 [(brcond (i32 (cond_op RO:$rs, 0)), bb:$offset)], II_BCCZ,
1505 class CBranchZeroLikely<string opstr, DAGOperand opnd, RegisterOperand RO> :
1506 InstSE<(outs), (ins RO:$rs, opnd:$offset),
1516 class SetCC_R<string opstr, PatFrag cond_op, RegisterOperand RO> :
1517 InstSE<(outs GPR32Opnd:$rd), (ins RO:$rs, RO:$rt),
1519 [(set GPR32Opnd:$rd, (cond_op RO:$rs, RO:$rt))],
1523 RegisterOperand RO>:
1524 InstSE<(outs GPR32Opnd:$rt), (ins RO:$rs, Od:$imm16),
1526 [(set GPR32Opnd:$rt, (cond_op RO:$rs, imm_type:$imm16))],
1557 class JumpFR<string opstr, RegisterOperand RO,
1559 InstSE<(outs), (ins RO:$rs), "jr\t$rs", [(operator RO:$rs)], II_JR,
1563 class IndirectBranch<string opstr, RegisterOperand RO> : JumpFR<opstr, RO> {
1576 class JumpLinkRegPseudo<RegisterOperand RO, Instruction JALRInst,
1577 Register RetReg, RegisterOperand ResRO = RO>:
1578 PseudoSE<(outs), (ins RO:$rs), [(MipsJmpLink RO:$rs)], II_JALR>,
1583 class JumpLinkReg<string opstr, RegisterOperand RO>:
1584 InstSE<(outs RO:$rd), (ins RO:$rs), !strconcat(opstr, "\t$rd, $rs"),
1590 RegisterOperand RO> :
1591 InstSE<(outs), (ins RO:$rs, opnd:$offset),
1604 class TailCallReg<Instruction JumpInst, RegisterOperand RO> :
1605 PseudoSE<(outs), (ins RO:$rs), [(MipsTailCall RO:$rs)], II_JR>,
1606 PseudoInstExpansion<(JumpInst RO:$rs)> {
1644 class DEI_FT<string opstr, RegisterOperand RO,
1646 InstSE<(outs RO:$rt), (ins),
1663 class TEQ_FT<string opstr, RegisterOperand RO, Operand ImmOp,
1665 InstSE<(outs), (ins RO:$rs, RO:$rt, ImmOp:$code_),
1668 class TEQI_FT<string opstr, RegisterOperand RO,
1670 InstSE<(outs), (ins RO:$rs, simm16:$imm16),
1675 class Mult<string opstr, InstrItinClass itin, RegisterOperand RO,
1677 InstSE<(outs), (ins RO:$rs, RO:$rt), !strconcat(opstr, "\t$rs, $rt"), [],
1711 class Div<string opstr, InstrItinClass itin, RegisterOperand RO,
1713 InstSE<(outs), (ins RO:$rs, RO:$rt), !strconcat(opstr, "\t$$zero, $rs, $rt"),
1723 class MoveFromLOHI<string opstr, RegisterOperand RO, Register UseReg>:
1724 InstSE<(outs RO:$rd), (ins), !strconcat(opstr, "\t$rd"), [], II_MFHI_MFLO,
1736 class MoveToLOHI<string opstr, RegisterOperand RO, list<Register> DefRegs>:
1737 InstSE<(outs), (ins RO:$rs), !strconcat(opstr, "\t$rs"), [], II_MTHI_MTLO,
1744 class EffectiveAddress<string opstr, RegisterOperand RO> :
1745 InstSE<(outs RO:$rt), (ins mem_ea:$addr), !strconcat(opstr, "\t$rt, $addr"),
1746 [(set RO:$rt, addr:$addr)], II_ADDIU, FrmI,
1754 class CountLeading0<string opstr, RegisterOperand RO,
1756 InstSE<(outs RO:$rd), (ins RO:$rs), !strconcat(opstr, "\t$rd, $rs"),
1757 [(set RO:$rd, (ctlz RO:$rs))], itin, FrmR, opstr>;
1759 class CountLeading1<string opstr, RegisterOperand RO,
1761 InstSE<(outs RO:$rd), (ins RO:$rs), !strconcat(opstr, "\t$rd, $rs"),
1762 [(set RO:$rd, (ctlz (not RO:$rs)))], itin, FrmR, opstr>;
1765 class SignExtInReg<string opstr, ValueType vt, RegisterOperand RO,
1767 InstSE<(outs RO:$rd), (ins RO:$rt), !strconcat(opstr, "\t$rd, $rt"),
1768 [(set RO:$rd, (sext_inreg RO:$rt, vt))], itin, FrmR, opstr>;
1771 class SubwordSwap<string opstr, RegisterOperand RO,
1773 InstSE<(outs RO:$rd), (ins RO:$rt), !strconcat(opstr, "\t$rd, $rt"), [], itin,
1779 class ReadHardware<RegisterOperand CPURegOperand, RegisterOperand RO> :
1780 InstSE<(outs CPURegOperand:$rt), (ins RO:$rd, uimm8:$sel),
1784 class ExtBase<string opstr, RegisterOperand RO, Operand PosOpnd,
1787 InstSE<(outs RO:$rt), (ins RO:$rs, PosOpnd:$pos, SizeOpnd:$size),
1789 [(set RO:$rt, (Op RO:$rs, PosImm:$pos, SizeImm:$size))], II_EXT,
1793 class InsBase<string opstr, RegisterOperand RO, Operand PosOpnd,
1795 InstSE<(outs RO:$rt), (ins RO:$rs, PosOpnd:$pos, SizeOpnd:$size, RO:$src),
1797 [(set RO:$rt, (null_frag RO:$rs, PosImm:$pos, SizeImm:$size,
1798 RO:$src))],
1842 class LLBase<string opstr, RegisterOperand RO, DAGOperand MO = mem> :
1843 InstSE<(outs RO:$rt), (ins MO:$addr), !strconcat(opstr, "\t$rt, $addr"),
1849 class SCBase<string opstr, RegisterOperand RO> :
1850 InstSE<(outs RO:$dst), (ins RO:$rt, mem:$addr),
1857 class MFC3OP<string asmstr, RegisterOperand RO, RegisterOperand RD,
1859 InstSE<(outs RO:$rt), (ins RD:$rd, uimm3:$sel),
1864 class MTC3OP<string asmstr, RegisterOperand RO, RegisterOperand RD,
1866 InstSE<(outs RO:$rd), (ins RD:$rt, uimm3:$sel),
2277 class PseudoIndirectBranchBase<Instruction JumpInst, RegisterOperand RO> :
2278 MipsPseudo<(outs), (ins RO:$rs), [(brind RO:$rs)],
2280 PseudoInstExpansion<(JumpInst RO:$rs)> {
2298 class PseudoReturnBase<RegisterOperand RO> : MipsPseudo<(outs), (ins RO:$rs),
2467 class JR_HB_DESC<RegisterOperand RO> :
2468 InstSE<(outs), (ins), "", [], II_JR_HB, FrmJ>, JR_HB_DESC_BASE<"jr.hb", RO> {
2477 class JALR_HB_DESC<RegisterOperand RO> :
2479 RO> {
2659 RegisterOperand RO = GPR32Opnd,
2662 (Opcode RO:$rs,
2663 RO:$rt,
2666 (Opcode RO:$rs,
2667 RO:$rs,
2916 class LoadImmediate32<string instr_asm, Operand Od, RegisterOperand RO> :
2917 MipsAsmPseudoInst<(outs RO:$rt), (ins Od:$imm32),
2922 RegisterOperand RO> :
2923 MipsAsmPseudoInst<(outs RO:$rt), (ins MemOpnd:$addr),
2927 class LoadAddressFromImm32<string instr_asm, Operand Od, RegisterOperand RO> :
2928 MipsAsmPseudoInst<(outs RO:$rt), (ins Od:$imm32),
2937 class NORIMM_DESC_BASE<RegisterOperand RO, DAGOperand Imm> :
2938 MipsAsmPseudoInst<(outs RO:$rs), (ins RO:$rt, Imm:$imm),