Lines Matching refs:MipsSubtarget
62 bool MipsSubtarget::DspWarningPrinted = false;
63 bool MipsSubtarget::MSAWarningPrinted = false;
64 bool MipsSubtarget::VirtWarningPrinted = false;
65 bool MipsSubtarget::CRCWarningPrinted = false;
66 bool MipsSubtarget::GINVWarningPrinted = false;
68 void MipsSubtarget::anchor() {} in anchor()
70 MipsSubtarget::MipsSubtarget(const Triple &TT, StringRef CPU, StringRef FS, in MipsSubtarget() function in MipsSubtarget
220 bool MipsSubtarget::isPositionIndependent() const { in isPositionIndependent()
225 bool MipsSubtarget::enablePostRAScheduler() const { return true; } in enablePostRAScheduler()
227 void MipsSubtarget::getCriticalPathRCs(RegClassVector &CriticalPathRCs) const { in getCriticalPathRCs()
233 CodeGenOpt::Level MipsSubtarget::getOptLevelToEnablePostRAScheduler() const { in getOptLevelToEnablePostRAScheduler()
237 MipsSubtarget &
238 MipsSubtarget::initializeSubtargetDependencies(StringRef CPU, StringRef FS, in initializeSubtargetDependencies()
266 bool MipsSubtarget::useConstantIslands() { in useConstantIslands()
272 Reloc::Model MipsSubtarget::getRelocationModel() const { in getRelocationModel()
276 bool MipsSubtarget::isABI_N64() const { return getABI().IsN64(); } in isABI_N64()
277 bool MipsSubtarget::isABI_N32() const { return getABI().IsN32(); } in isABI_N32()
278 bool MipsSubtarget::isABI_O32() const { return getABI().IsO32(); } in isABI_O32()
279 const MipsABIInfo &MipsSubtarget::getABI() const { return TM.getABI(); } in getABI()
281 const CallLowering *MipsSubtarget::getCallLowering() const { in getCallLowering()
285 const LegalizerInfo *MipsSubtarget::getLegalizerInfo() const { in getLegalizerInfo()
289 const RegisterBankInfo *MipsSubtarget::getRegBankInfo() const { in getRegBankInfo()
293 InstructionSelector *MipsSubtarget::getInstructionSelector() const { in getInstructionSelector()