Lines Matching refs:OpNode
166 multiclass I3<string OpcStr, SDNode OpNode> {
170 [(set Int64Regs:$dst, (OpNode Int64Regs:$a, Int64Regs:$b))]>;
174 [(set Int64Regs:$dst, (OpNode Int64Regs:$a, imm:$b))]>;
178 [(set Int32Regs:$dst, (OpNode Int32Regs:$a, Int32Regs:$b))]>;
182 [(set Int32Regs:$dst, (OpNode Int32Regs:$a, imm:$b))]>;
186 [(set Int16Regs:$dst, (OpNode Int16Regs:$a, Int16Regs:$b))]>;
190 [(set Int16Regs:$dst, (OpNode Int16Regs:$a, (imm):$b))]>;
195 multiclass ADD_SUB_INT_32<string OpcStr, SDNode OpNode> {
199 [(set Int32Regs:$dst, (OpNode Int32Regs:$a, Int32Regs:$b))]>;
203 [(set Int32Regs:$dst, (OpNode Int32Regs:$a, imm:$b))]>;
215 multiclass F3<string OpcStr, SDNode OpNode> {
220 [(set Float64Regs:$dst, (OpNode Float64Regs:$a, Float64Regs:$b))]>;
225 [(set Float64Regs:$dst, (OpNode Float64Regs:$a, fpimm:$b))]>;
230 [(set Float32Regs:$dst, (OpNode Float32Regs:$a, Float32Regs:$b))]>,
236 [(set Float32Regs:$dst, (OpNode Float32Regs:$a, fpimm:$b))]>,
242 [(set Float32Regs:$dst, (OpNode Float32Regs:$a, Float32Regs:$b))]>;
247 [(set Float32Regs:$dst, (OpNode Float32Regs:$a, fpimm:$b))]>;
259 multiclass F3_fma_component<string OpcStr, SDNode OpNode> {
264 [(set Float64Regs:$dst, (OpNode Float64Regs:$a, Float64Regs:$b))]>,
270 [(set Float64Regs:$dst, (OpNode Float64Regs:$a, fpimm:$b))]>,
276 [(set Float32Regs:$dst, (OpNode Float32Regs:$a, Float32Regs:$b))]>,
282 [(set Float32Regs:$dst, (OpNode Float32Regs:$a, fpimm:$b))]>,
288 [(set Float32Regs:$dst, (OpNode Float32Regs:$a, Float32Regs:$b))]>,
294 [(set Float32Regs:$dst, (OpNode Float32Regs:$a, fpimm:$b))]>,
301 [(set Float16Regs:$dst, (OpNode Float16Regs:$a, Float16Regs:$b))]>,
307 [(set Float16Regs:$dst, (OpNode Float16Regs:$a, Float16Regs:$b))]>,
314 [(set Float16x2Regs:$dst, (OpNode Float16x2Regs:$a, Float16x2Regs:$b))]>,
320 [(set Float16x2Regs:$dst, (OpNode Float16x2Regs:$a, Float16x2Regs:$b))]>,
328 [(set Float64Regs:$dst, (OpNode Float64Regs:$a, Float64Regs:$b))]>,
334 [(set Float64Regs:$dst, (OpNode Float64Regs:$a, fpimm:$b))]>,
340 [(set Float32Regs:$dst, (OpNode Float32Regs:$a, Float32Regs:$b))]>,
346 [(set Float32Regs:$dst, (OpNode Float32Regs:$a, fpimm:$b))]>,
352 [(set Float32Regs:$dst, (OpNode Float32Regs:$a, Float32Regs:$b))]>,
358 [(set Float32Regs:$dst, (OpNode Float32Regs:$a, fpimm:$b))]>,
364 [(set Float16Regs:$dst, (OpNode Float16Regs:$a, Float16Regs:$b))]>,
370 [(set Float16Regs:$dst, (OpNode Float16Regs:$a, Float16Regs:$b))]>,
376 [(set Float16x2Regs:$dst, (OpNode Float16x2Regs:$a, Float16x2Regs:$b))]>,
382 [(set Float16x2Regs:$dst, (OpNode Float16x2Regs:$a, Float16x2Regs:$b))]>,
389 multiclass F2<string OpcStr, SDNode OpNode> {
392 [(set Float64Regs:$dst, (OpNode Float64Regs:$a))]>;
395 [(set Float32Regs:$dst, (OpNode Float32Regs:$a))]>,
399 [(set Float32Regs:$dst, (OpNode Float32Regs:$a))]>;
506 multiclass ADD_SUB_i1<SDNode OpNode> {
509 [(set Int1Regs:$dst, (OpNode Int1Regs:$a, Int1Regs:$b))]>;
512 [(set Int1Regs:$dst, (OpNode Int1Regs:$a, (imm):$b))]>;
1083 multiclass BITWISE<string OpcStr, SDNode OpNode> {
1087 [(set Int1Regs:$dst, (OpNode Int1Regs:$a, Int1Regs:$b))]>;
1091 [(set Int1Regs:$dst, (OpNode Int1Regs:$a, imm:$b))]>;
1095 [(set Int16Regs:$dst, (OpNode Int16Regs:$a, Int16Regs:$b))]>;
1099 [(set Int16Regs:$dst, (OpNode Int16Regs:$a, imm:$b))]>;
1103 [(set Int32Regs:$dst, (OpNode Int32Regs:$a, Int32Regs:$b))]>;
1107 [(set Int32Regs:$dst, (OpNode Int32Regs:$a, imm:$b))]>;
1111 [(set Int64Regs:$dst, (OpNode Int64Regs:$a, Int64Regs:$b))]>;
1115 [(set Int64Regs:$dst, (OpNode Int64Regs:$a, imm:$b))]>;
1140 multiclass SHIFT<string OpcStr, SDNode OpNode> {
1144 [(set Int64Regs:$dst, (OpNode Int64Regs:$a, Int32Regs:$b))]>;
1148 [(set Int64Regs:$dst, (OpNode Int64Regs:$a, (i32 imm:$b)))]>;
1152 [(set Int32Regs:$dst, (OpNode Int32Regs:$a, Int32Regs:$b))]>;
1156 [(set Int32Regs:$dst, (OpNode Int32Regs:$a, (i32 imm:$b)))]>;
1160 [(set Int32Regs:$dst, (OpNode (i32 imm:$a), (i32 imm:$b)))]>;
1164 [(set Int16Regs:$dst, (OpNode Int16Regs:$a, Int32Regs:$b))]>;
1168 [(set Int16Regs:$dst, (OpNode Int16Regs:$a, (i32 imm:$b)))]>;
1637 multiclass ISET_FORMAT<PatFrag OpNode, PatLeaf Mode,
1657 def : Pat<(i1 (OpNode Int16Regs:$a, Int16Regs:$b)),
1659 def : Pat<(i1 (OpNode Int16Regs:$a, imm:$b)),
1661 def : Pat<(i1 (OpNode imm:$a, Int16Regs:$b)),
1664 def : Pat<(i1 (OpNode Int32Regs:$a, Int32Regs:$b)),
1666 def : Pat<(i1 (OpNode Int32Regs:$a, imm:$b)),
1668 def : Pat<(i1 (OpNode imm:$a, Int32Regs:$b)),
1671 def : Pat<(i1 (OpNode Int64Regs:$a, Int64Regs:$b)),
1673 def : Pat<(i1 (OpNode Int64Regs:$a, imm:$b)),
1675 def : Pat<(i1 (OpNode imm:$a, Int64Regs:$b)),
1679 def : Pat<(i32 (OpNode Int16Regs:$a, Int16Regs:$b)),
1681 def : Pat<(i32 (OpNode Int16Regs:$a, imm:$b)),
1683 def : Pat<(i32 (OpNode imm:$a, Int16Regs:$b)),
1686 def : Pat<(i32 (OpNode Int32Regs:$a, Int32Regs:$b)),
1688 def : Pat<(i32 (OpNode Int32Regs:$a, imm:$b)),
1690 def : Pat<(i32 (OpNode imm:$a, Int32Regs:$b)),
1693 def : Pat<(i32 (OpNode Int64Regs:$a, Int64Regs:$b)),
1695 def : Pat<(i32 (OpNode Int64Regs:$a, imm:$b)),
1697 def : Pat<(i32 (OpNode imm:$a, Int64Regs:$b)),
1701 multiclass ISET_FORMAT_SIGNED<PatFrag OpNode, PatLeaf Mode>
1702 : ISET_FORMAT<OpNode, Mode,
1713 multiclass ISET_FORMAT_UNSIGNED<PatFrag OpNode, PatLeaf Mode>
1714 : ISET_FORMAT<OpNode, Mode,
1757 multiclass FSET_FORMAT<PatFrag OpNode, PatLeaf Mode, PatLeaf ModeFTZ> {
1759 def : Pat<(i1 (OpNode Float16Regs:$a, Float16Regs:$b)),
1762 def : Pat<(i1 (OpNode Float16Regs:$a, Float16Regs:$b)),
1765 def : Pat<(i1 (OpNode Float16Regs:$a, fpimm:$b)),
1768 def : Pat<(i1 (OpNode Float16Regs:$a, fpimm:$b)),
1771 def : Pat<(i1 (OpNode fpimm:$a, Float16Regs:$b)),
1774 def : Pat<(i1 (OpNode fpimm:$a, Float16Regs:$b)),
1779 def : Pat<(i1 (OpNode Float32Regs:$a, Float32Regs:$b)),
1782 def : Pat<(i1 (OpNode Float32Regs:$a, Float32Regs:$b)),
1784 def : Pat<(i1 (OpNode Float32Regs:$a, fpimm:$b)),
1787 def : Pat<(i1 (OpNode Float32Regs:$a, fpimm:$b)),
1789 def : Pat<(i1 (OpNode fpimm:$a, Float32Regs:$b)),
1792 def : Pat<(i1 (OpNode fpimm:$a, Float32Regs:$b)),
1796 def : Pat<(i1 (OpNode Float64Regs:$a, Float64Regs:$b)),
1798 def : Pat<(i1 (OpNode Float64Regs:$a, fpimm:$b)),
1800 def : Pat<(i1 (OpNode fpimm:$a, Float64Regs:$b)),
1804 def : Pat<(i32 (OpNode Float16Regs:$a, Float16Regs:$b)),
1807 def : Pat<(i32 (OpNode Float16Regs:$a, Float16Regs:$b)),
1810 def : Pat<(i32 (OpNode Float16Regs:$a, fpimm:$b)),
1813 def : Pat<(i32 (OpNode Float16Regs:$a, fpimm:$b)),
1816 def : Pat<(i32 (OpNode fpimm:$a, Float16Regs:$b)),
1819 def : Pat<(i32 (OpNode fpimm:$a, Float16Regs:$b)),
1824 def : Pat<(i32 (OpNode Float32Regs:$a, Float32Regs:$b)),
1827 def : Pat<(i32 (OpNode Float32Regs:$a, Float32Regs:$b)),
1829 def : Pat<(i32 (OpNode Float32Regs:$a, fpimm:$b)),
1832 def : Pat<(i32 (OpNode Float32Regs:$a, fpimm:$b)),
1834 def : Pat<(i32 (OpNode fpimm:$a, Float32Regs:$b)),
1837 def : Pat<(i32 (OpNode fpimm:$a, Float32Regs:$b)),
1841 def : Pat<(i32 (OpNode Float64Regs:$a, Float64Regs:$b)),
1843 def : Pat<(i32 (OpNode Float64Regs:$a, fpimm:$b)),
1845 def : Pat<(i32 (OpNode fpimm:$a, Float64Regs:$b)),
2058 multiclass CALL<string OpcStr, SDNode OpNode> {
2060 !strconcat(OpcStr, " "), [(OpNode (i32 0))]>;
2062 !strconcat(OpcStr, " (retval0), "), [(OpNode (i32 1))]>;
2064 !strconcat(OpcStr, " (retval0, retval1), "), [(OpNode (i32 2))]>;
2066 !strconcat(OpcStr, " (retval0, retval1, retval2), "), [(OpNode (i32 3))]>;
2069 [(OpNode (i32 4))]>;
2072 [(OpNode (i32 5))]>;
2076 [(OpNode (i32 6))]>;
2080 [(OpNode (i32 7))]>;
2084 [(OpNode (i32 8))]>;