Lines Matching refs:isReg
48 if (MO.isReg() || MO.isImm()) in getDirectBrEncoding()
63 if (MO.isReg() || MO.isImm()) return getMachineOpValue(MI, MO, Fixups, STI); in getCondBrEncoding()
76 if (MO.isReg() || MO.isImm()) return getMachineOpValue(MI, MO, Fixups, STI); in getAbsDirectBrEncoding()
89 if (MO.isReg() || MO.isImm()) return getMachineOpValue(MI, MO, Fixups, STI); in getAbsCondBrEncoding()
101 assert(MI.getOperand(OpNo).isReg() && "Operand should be a register"); in getVSRpEvenEncoding()
111 if (MO.isReg() || MO.isImm()) return getMachineOpValue(MI, MO, Fixups, STI); in getImm16Encoding()
124 assert(!MO.isReg() && "Not expecting a register for this operand."); in getImm34Encoding()
154 assert(MI.getOperand(OpNo+1).isReg()); in getMemRIEncoding()
172 assert(MI.getOperand(OpNo+1).isReg()); in getMemRIXEncoding()
190 assert(MI.getOperand(OpNo+1).isReg()); in getMemRIX16Encoding()
302 assert(MI.getOperand(OpNo + 1).isReg() && "Expecting a register."); in getMemRI34Encoding()
315 assert(MI.getOperand(OpNo+1).isReg()); in getSPE8DisEncoding()
330 assert(MI.getOperand(OpNo+1).isReg()); in getSPE4DisEncoding()
345 assert(MI.getOperand(OpNo+1).isReg()); in getSPE2DisEncoding()
358 if (MO.isReg()) return getMachineOpValue(MI, MO, Fixups, STI); in getTLSRegEncoding()
415 if (MO.isReg()) { in getMachineOpValue()