207       MachineOperand &FalseValue = (*I)->getOperand(2);  in expandAndMergeISELs()  local
213           useSameRegister(Dest, FalseValue)) {  in expandAndMergeISELs()
222       } else if (useSameRegister(TrueValue, FalseValue)) {  in expandAndMergeISELs()
237             .add(FalseValue);  in expandAndMergeISELs()
274     MachineOperand &FalseValue = (*MI)->getOperand(2);  in handleSpecialCases()  local
283     bool IsORIInstRequired = !useSameRegister(Dest, FalseValue);  in handleSpecialCases()
305     if (useSameRegister(TrueValue, FalseValue) && (BIL.size() == 1)) {  in handleSpecialCases()
314           .add(FalseValue);  in handleSpecialCases()
431     MachineOperand &FalseValue = MI->getOperand(2); // Value to store if  in populateBlocks()  local
436     LLVM_DEBUG(dbgs() << "FalseValue: " << FalseValue << "\n");  in populateBlocks()
442     bool IsORIInstRequired = !useSameRegister(Dest, FalseValue);  in populateBlocks()
457           .add(FalseValue)  in populateBlocks()