206       MachineOperand &TrueValue = (*I)->getOperand(1);  in expandAndMergeISELs()  local
212       if (useSameRegister(Dest, TrueValue) &&  in expandAndMergeISELs()
222       } else if (useSameRegister(TrueValue, FalseValue)) {  in expandAndMergeISELs()
236             .add(TrueValue)  in expandAndMergeISELs()
273     MachineOperand &TrueValue = (*MI)->getOperand(1);  in handleSpecialCases()  local
282     bool IsADDIInstRequired = !useSameRegister(Dest, TrueValue);  in handleSpecialCases()
305     if (useSameRegister(TrueValue, FalseValue) && (BIL.size() == 1)) {  in handleSpecialCases()
313           .add(TrueValue)  in handleSpecialCases()
429     MachineOperand &TrueValue = MI->getOperand(1);  // Value to store if  in populateBlocks()  local
435     LLVM_DEBUG(dbgs() << "TrueValue: " << TrueValue << "\n");  in populateBlocks()
441     bool IsADDIInstRequired = !useSameRegister(Dest, TrueValue);  in populateBlocks()
449           .add(TrueValue)  in populateBlocks()