733       if (Subtarget.hasP8Altivec() && (VT.SimpleTy != MVT::v1i128)) {  in PPCTargetLowering()
743       if (Subtarget.hasP9Altivec() && (VT.SimpleTy != MVT::v1i128))  in PPCTargetLowering()
856     setOperationAction(ISD::ROTL, MVT::v1i128, Custom);  in PPCTargetLowering()
897       setOperationAction(ISD::UREM, MVT::v1i128, Legal);  in PPCTargetLowering()
898       setOperationAction(ISD::SREM, MVT::v1i128, Legal);  in PPCTargetLowering()
899       setOperationAction(ISD::UDIV, MVT::v1i128, Legal);  in PPCTargetLowering()
900       setOperationAction(ISD::SDIV, MVT::v1i128, Legal);  in PPCTargetLowering()
901       setOperationAction(ISD::ROTL, MVT::v1i128, Legal);  in PPCTargetLowering()
997         setOperationAction(ISD::SHL, MVT::v1i128, Expand);  in PPCTargetLowering()
998         setOperationAction(ISD::SRL, MVT::v1i128, Expand);  in PPCTargetLowering()
999         setOperationAction(ISD::SRA, MVT::v1i128, Expand);  in PPCTargetLowering()
1016         setOperationAction(ISD::SETCC, MVT::v1i128, Legal);  in PPCTargetLowering()
1018         setOperationAction(ISD::SETCC, MVT::v1i128, Expand);  in PPCTargetLowering()
1103       addRegisterClass(MVT::v1i128, &PPC::VRRCRegClass);  in PPCTargetLowering()
1113       setOperationAction(ISD::SHL, MVT::v1i128, Legal);  in PPCTargetLowering()
1114       setOperationAction(ISD::SRL, MVT::v1i128, Legal);  in PPCTargetLowering()
1115       setOperationAction(ISD::SRA, MVT::v1i128, Expand);  in PPCTargetLowering()
1174       setOperationAction(ISD::BSWAP, MVT::v1i128, Legal);  in PPCTargetLowering()
1233     setOperationAction(ISD::SRA, MVT::v1i128, Legal);  in PPCTargetLowering()
3618       ArgVT == MVT::v1i128 || ArgVT == MVT::f128)  in CalculateStackSlotAlignment()
3687         ArgVT == MVT::v1i128 || ArgVT == MVT::f128)  in CalculateStackSlotUsed()
4290     case MVT::v1i128:  in LowerFormalArguments_64SVR4()
6145         case MVT::v1i128:  in LowerCall_64SVR4()
6515     case MVT::v1i128:  in LowerCall_64SVR4()
7137   case MVT::v1i128: {  in CC_AIX()
7176   case MVT::v1i128:  in getRegClassForSVT()
9931   assert(Op.getValueType() == MVT::v1i128 &&  in LowerROTL()
9944       return DAG.getNode(ISD::BITCAST, dl, MVT::v1i128, Shuffle);  in LowerROTL()
9952   return DAG.getNode(ISD::BITCAST, dl, MVT::v1i128, OROp);  in LowerROTL()
10108       SDValue Conv = DAG.getNode(ISD::BITCAST, dl, MVT::v1i128, V1);  in LowerVECTOR_SHUFFLE()
10109       SDValue ReveQWord = DAG.getNode(ISD::BSWAP, dl, MVT::v1i128, Conv);  in LowerVECTOR_SHUFFLE()
14066   if (N->getValueType(0) != MVT::v1i128)  in combineBVZEXTLOAD()
14094                                  DAG.getVTList(MVT::v1i128, MVT::Other),  in combineBVZEXTLOAD()