1099                                    Register FalseReg, int &CondCycles,  in canInsertSelect()  argument
1112     RI.getCommonSubClass(MRI.getRegClass(TrueReg), MRI.getRegClass(FalseReg));  in canInsertSelect()
1138                                 Register FalseReg) const {  in insertSelect()
1145     RI.getCommonSubClass(MRI.getRegClass(TrueReg), MRI.getRegClass(FalseReg));  in insertSelect()
1197   Register FirstReg =  SwapOps ? FalseReg : TrueReg,  in insertSelect()
1198            SecondReg = SwapOps ? TrueReg  : FalseReg;  in insertSelect()
2664                           unsigned TrueReg, unsigned FalseReg,  in selectReg()  argument
2671       return Imm1 < Imm2 ? TrueReg : FalseReg;  in selectReg()
2673       return Imm1 > Imm2 ? TrueReg : FalseReg;  in selectReg()
2675       return Imm1 == Imm2 ? TrueReg : FalseReg;  in selectReg()
2683       return (uint64_t)Imm1 < (uint64_t)Imm2 ? TrueReg : FalseReg;  in selectReg()
2685       return (uint64_t)Imm1 > (uint64_t)Imm2 ? TrueReg : FalseReg;  in selectReg()
2687       return Imm1 == Imm2 ? TrueReg : FalseReg;  in selectReg()
4098       Register FalseReg = CompareUseMI.getOperand(2).getReg();  in simplifyToLI()  local
4100           selectReg(SExtImm, SExtComparand, Opc, TrueReg, FalseReg, CRSubReg);  in simplifyToLI()