Lines Matching refs:RISCVAsmBackend

26 Optional<MCFixupKind> RISCVAsmBackend::getFixupKind(StringRef Name) const {  in getFixupKind()
41 RISCVAsmBackend::getFixupKindInfo(MCFixupKind Kind) const {  in getFixupKindInfo()
90 bool RISCVAsmBackend::shouldForceRelocation(const MCAssembler &Asm,  in shouldForceRelocation()
114 bool RISCVAsmBackend::fixupNeedsRelaxationAdvanced(const MCFixup &Fixup,  in fixupNeedsRelaxationAdvanced()
142 void RISCVAsmBackend::relaxInstruction(MCInst &Inst,  in relaxInstruction()
181 unsigned RISCVAsmBackend::getRelaxedOpcode(unsigned Op) const {  in getRelaxedOpcode()
195 bool RISCVAsmBackend::mayNeedRelaxation(const MCInst &Inst,  in mayNeedRelaxation()
200 bool RISCVAsmBackend::writeNopData(raw_ostream &OS, uint64_t Count) const {  in writeNopData()
319 bool RISCVAsmBackend::evaluateTargetFixup(  in evaluateTargetFixup()
380 void RISCVAsmBackend::applyFixup(const MCAssembler &Asm, const MCFixup &Fixup,  in applyFixup()
414 bool RISCVAsmBackend::shouldInsertExtraNopBytesForCodeAlign(  in shouldInsertExtraNopBytesForCodeAlign()
436 bool RISCVAsmBackend::shouldInsertFixupForCodeAlign(MCAssembler &Asm,  in shouldInsertFixupForCodeAlign()
465 RISCVAsmBackend::createObjectTargetWriter() const {  in createObjectTargetWriter()
475   return new RISCVAsmBackend(STI, OSABI, TT.isArch64Bit(), Options);  in createRISCVAsmBackend()