44 RISCVTargetLowering::RISCVTargetLowering(const TargetMachine &TM,  in RISCVTargetLowering()  function in RISCVTargetLowering
356 EVT RISCVTargetLowering::getSetCCResultType(const DataLayout &DL, LLVMContext &,  in getSetCCResultType()
363 bool RISCVTargetLowering::getTgtMemIntrinsic(IntrinsicInfo &Info,  in getTgtMemIntrinsic()
391 bool RISCVTargetLowering::isLegalAddressingMode(const DataLayout &DL,  in isLegalAddressingMode()
417 bool RISCVTargetLowering::isLegalICmpImmediate(int64_t Imm) const {  in isLegalICmpImmediate()
421 bool RISCVTargetLowering::isLegalAddImmediate(int64_t Imm) const {  in isLegalAddImmediate()
428 bool RISCVTargetLowering::isTruncateFree(Type *SrcTy, Type *DstTy) const {  in isTruncateFree()
436 bool RISCVTargetLowering::isTruncateFree(EVT SrcVT, EVT DstVT) const {  in isTruncateFree()
445 bool RISCVTargetLowering::isZExtFree(SDValue Val, EVT VT2) const {  in isZExtFree()
459 bool RISCVTargetLowering::isSExtCheaperThanZExt(EVT SrcVT, EVT DstVT) const {  in isSExtCheaperThanZExt()
463 bool RISCVTargetLowering::isCheapToSpeculateCttz() const {  in isCheapToSpeculateCttz()
467 bool RISCVTargetLowering::isCheapToSpeculateCtlz() const {  in isCheapToSpeculateCtlz()
471 bool RISCVTargetLowering::isFPImmLegal(const APFloat &Imm, EVT VT,  in isFPImmLegal()
484 bool RISCVTargetLowering::hasBitPreservingFPLogic(EVT VT) const {  in hasBitPreservingFPLogic()
529 SDValue RISCVTargetLowering::LowerOperation(SDValue Op,  in LowerOperation()
617 SDValue RISCVTargetLowering::getAddr(NodeTy *N, SelectionDAG &DAG,  in getAddr()
657 SDValue RISCVTargetLowering::lowerGlobalAddress(SDValue Op,  in lowerGlobalAddress()
679 SDValue RISCVTargetLowering::lowerBlockAddress(SDValue Op,  in lowerBlockAddress()
686 SDValue RISCVTargetLowering::lowerConstantPool(SDValue Op,  in lowerConstantPool()
693 SDValue RISCVTargetLowering::getStaticTLSAddr(GlobalAddressSDNode *N,  in getStaticTLSAddr()
734 SDValue RISCVTargetLowering::getDynamicTLSAddr(GlobalAddressSDNode *N,  in getDynamicTLSAddr()
766 SDValue RISCVTargetLowering::lowerGlobalTLSAddress(SDValue Op,  in lowerGlobalTLSAddress()
804 SDValue RISCVTargetLowering::lowerSELECT(SDValue Op, SelectionDAG &DAG) const {  in lowerSELECT()
842 SDValue RISCVTargetLowering::lowerVASTART(SDValue Op, SelectionDAG &DAG) const {  in lowerVASTART()
857 SDValue RISCVTargetLowering::lowerFRAMEADDR(SDValue Op,  in lowerFRAMEADDR()
880 SDValue RISCVTargetLowering::lowerRETURNADDR(SDValue Op,  in lowerRETURNADDR()
910 SDValue RISCVTargetLowering::lowerShiftLeftParts(SDValue Op,  in lowerShiftLeftParts()
949 SDValue RISCVTargetLowering::lowerShiftRightParts(SDValue Op, SelectionDAG &DAG,  in lowerShiftRightParts()
1001 SDValue RISCVTargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue Op,  in LowerINTRINSIC_WO_CHAIN()
1071 void RISCVTargetLowering::ReplaceNodeResults(SDNode *N,  in ReplaceNodeResults()
1444 SDValue RISCVTargetLowering::PerformDAGCombine(SDNode *N,  in PerformDAGCombine()
1586 bool RISCVTargetLowering::isDesirableToCommuteWithShift(  in isDesirableToCommuteWithShift()
1632 unsigned RISCVTargetLowering::ComputeNumSignBitsForTargetNode(  in ComputeNumSignBitsForTargetNode()
1969 RISCVTargetLowering::EmitInstrWithCustomInserter(MachineInstr &MI,  in EmitInstrWithCustomInserter()
2259 void RISCVTargetLowering::analyzeInputArgs(  in analyzeInputArgs()
2285 void RISCVTargetLowering::analyzeOutputArgs(  in analyzeOutputArgs()
2567 SDValue RISCVTargetLowering::LowerFormalArguments(  in LowerFormalArguments()
2720 bool RISCVTargetLowering::isEligibleForTailCallOptimization(  in isEligibleForTailCallOptimization()
2792 SDValue RISCVTargetLowering::LowerCall(CallLoweringInfo &CLI,  in LowerCall()
3069 bool RISCVTargetLowering::CanLowerReturn(  in CanLowerReturn()
3086 RISCVTargetLowering::LowerReturn(SDValue Chain, CallingConv::ID CallConv,  in LowerReturn()
3187 void RISCVTargetLowering::validateCCReservedRegs(  in validateCCReservedRegs()
3200 bool RISCVTargetLowering::mayBeEmittedAsTailCall(const CallInst *CI) const {  in mayBeEmittedAsTailCall()
3204 const char *RISCVTargetLowering::getTargetNodeName(unsigned Opcode) const {  in getTargetNodeName()
3248 RISCVTargetLowering::ConstraintType
3249 RISCVTargetLowering::getConstraintType(StringRef Constraint) const {  in getConstraintType()
3268 RISCVTargetLowering::getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI,  in getRegForInlineAsmConstraint()
3388 RISCVTargetLowering::getInlineAsmMemConstraint(StringRef ConstraintCode) const {  in getInlineAsmMemConstraint()
3402 void RISCVTargetLowering::LowerAsmOperandForConstraint(  in LowerAsmOperandForConstraint()
3440 Instruction *RISCVTargetLowering::emitLeadingFence(IRBuilder<> &Builder,  in emitLeadingFence()
3450 Instruction *RISCVTargetLowering::emitTrailingFence(IRBuilder<> &Builder,  in emitTrailingFence()
3459 RISCVTargetLowering::shouldExpandAtomicRMWInIR(AtomicRMWInst *AI) const {  in shouldExpandAtomicRMWInIR()
3523 Value *RISCVTargetLowering::emitMaskedAtomicRMWIntrinsic(  in emitMaskedAtomicRMWIntrinsic()
3567 RISCVTargetLowering::shouldExpandAtomicCmpXchgInIR(  in shouldExpandAtomicCmpXchgInIR()
3575 Value *RISCVTargetLowering::emitMaskedAtomicCmpXchgIntrinsic(  in emitMaskedAtomicCmpXchgIntrinsic()
3597 bool RISCVTargetLowering::isFMAFasterThanFMulAndFAdd(const MachineFunction &MF,  in isFMAFasterThanFMulAndFAdd()
3618 Register RISCVTargetLowering::getExceptionPointerRegister(  in getExceptionPointerRegister()
3623 Register RISCVTargetLowering::getExceptionSelectorRegister(  in getExceptionSelectorRegister()
3628 bool RISCVTargetLowering::shouldExtendTypeInLibCall(EVT Type) const {  in shouldExtendTypeInLibCall()
3638 bool RISCVTargetLowering::decomposeMulByConstant(LLVMContext &Context, EVT VT,  in decomposeMulByConstant()
3662 RISCVTargetLowering::getRegisterByName(const char *RegName, LLT VT,  in getRegisterByName()