Lines Matching full:imm
23 return isUInt<6>(Imm) && (Imm != 0);
24 return isUInt<5>(Imm) && (Imm != 0);
30 int64_t Imm;
31 if (!MCOp.evaluateAsConstantImm(Imm))
34 return isUInt<6>(Imm) && (Imm != 0);
35 return isUInt<5>(Imm) && (Imm != 0);
39 def simm6 : Operand<XLenVT>, ImmLeaf<XLenVT, [{return isInt<6>(Imm);}]> {
44 int64_t Imm;
45 if (MCOp.evaluateAsConstantImm(Imm))
46 return isInt<6>(Imm);
52 ImmLeaf<XLenVT, [{return (Imm != 0) && isInt<6>(Imm);}]> {
57 int64_t Imm;
58 if (MCOp.evaluateAsConstantImm(Imm))
59 return (Imm != 0) && isInt<6>(Imm);
65 ImmLeaf<XLenVT, [{return (Imm == 0);}]> {
82 ImmLeaf<XLenVT, [{return (Imm != 0) &&
83 (isUInt<5>(Imm) ||
84 (Imm >= 0xfffe0 && Imm <= 0xfffff));}]> {
89 int64_t Imm;
90 if (MCOp.evaluateAsConstantImm(Imm))
91 return (Imm != 0) && (isUInt<5>(Imm) ||
92 (Imm >= 0xfffe0 && Imm <= 0xfffff));
99 ImmLeaf<XLenVT, [{return isShiftedUInt<5, 2>(Imm);}]> {
104 int64_t Imm;
105 if (!MCOp.evaluateAsConstantImm(Imm))
107 return isShiftedUInt<5, 2>(Imm);
113 ImmLeaf<XLenVT, [{return isShiftedUInt<6, 2>(Imm);}]> {
118 int64_t Imm;
119 if (!MCOp.evaluateAsConstantImm(Imm))
121 return isShiftedUInt<6, 2>(Imm);
127 ImmLeaf<XLenVT, [{return isShiftedUInt<5, 3>(Imm);}]> {
132 int64_t Imm;
133 if (!MCOp.evaluateAsConstantImm(Imm))
135 return isShiftedUInt<5, 3>(Imm);
141 ImmLeaf<XLenVT, [{return isShiftedInt<8, 1>(Imm);}]> {
147 int64_t Imm;
148 if (MCOp.evaluateAsConstantImm(Imm))
149 return isShiftedInt<8, 1>(Imm);
158 ImmLeaf<XLenVT, [{return isShiftedUInt<6, 3>(Imm);}]> {
163 int64_t Imm;
164 if (!MCOp.evaluateAsConstantImm(Imm))
166 return isShiftedUInt<6, 3>(Imm);
174 [{return isShiftedUInt<8, 2>(Imm) && (Imm != 0);}]> {
179 int64_t Imm;
180 if (!MCOp.evaluateAsConstantImm(Imm))
182 return isShiftedUInt<8, 2>(Imm) && (Imm != 0);
189 [{return (Imm != 0) && isShiftedInt<6, 4>(Imm);}]> {
194 int64_t Imm;
195 if (!MCOp.evaluateAsConstantImm(Imm))
197 return isShiftedInt<6, 4>(Imm) && (Imm != 0);
203 ImmLeaf<XLenVT, [{return isShiftedInt<11, 1>(Imm);}]> {
209 int64_t Imm;
210 if (MCOp.evaluateAsConstantImm(Imm))
211 return isShiftedInt<11, 1>(Imm);
224 : RVInst16CI<funct3, 0b10, (outs cls:$rd), (ins SP:$rs1, opnd:$imm),
225 OpcodeStr, "$rd, ${imm}(${rs1})">;
230 : RVInst16CSS<funct3, 0b10, (outs), (ins cls:$rs2, SP:$rs1, opnd:$imm),
231 OpcodeStr, "$rs2, ${imm}(${rs1})">;
236 : RVInst16CL<funct3, 0b00, (outs cls:$rd), (ins GPRC:$rs1, opnd:$imm),
237 OpcodeStr, "$rd, ${imm}(${rs1})">;
242 : RVInst16CS<funct3, 0b00, (outs), (ins cls:$rs2, GPRC:$rs1, opnd:$imm),
243 OpcodeStr, "$rs2, ${imm}(${rs1})">;
248 : RVInst16CB<funct3, 0b01, (outs), (ins cls:$rs1, simm9_lsb0:$imm),
249 OpcodeStr, "$rs1, $imm"> {
252 let Inst{12} = imm{7};
253 let Inst{11-10} = imm{3-2};
254 let Inst{6-5} = imm{6-5};
255 let Inst{4-3} = imm{1-0};
256 let Inst{2} = imm{4};
262 : RVInst16CB<0b100, 0b01, (outs cls:$rs1_wb), (ins cls:$rs1, ImmOpnd:$imm),
263 OpcodeStr, "$rs1, $imm"> {
265 let Inst{12} = imm{5};
267 let Inst{6-2} = imm{4-0};
288 (ins SP:$rs1, uimm10_lsb00nonzero:$imm),
289 "c.addi4spn", "$rd, $rs1, $imm">,
292 let Inst{12-11} = imm{5-4};
293 let Inst{10-7} = imm{9-6};
294 let Inst{6} = imm{2};
295 let Inst{5} = imm{3};
301 bits<8> imm;
302 let Inst{12-10} = imm{5-3};
303 let Inst{6-5} = imm{7-6};
308 bits<7> imm;
309 let Inst{12-10} = imm{5-3};
310 let Inst{6} = imm{2};
311 let Inst{5} = imm{6};
318 bits<7> imm;
319 let Inst{12-10} = imm{5-3};
320 let Inst{6} = imm{2};
321 let Inst{5} = imm{6};
327 bits<8> imm;
328 let Inst{12-10} = imm{5-3};
329 let Inst{6-5} = imm{7-6};
335 bits<8> imm;
336 let Inst{12-10} = imm{5-3};
337 let Inst{6-5} = imm{7-6};
342 bits<7> imm;
343 let Inst{12-10} = imm{5-3};
344 let Inst{6} = imm{2};
345 let Inst{5} = imm{6};
352 bits<7> imm;
353 let Inst{12-10} = imm{5-3};
354 let Inst{6} = imm{2};
355 let Inst{5} = imm{6};
361 bits<8> imm;
362 let Inst{12-10} = imm{5-3};
363 let Inst{6-5} = imm{7-6};
366 let rd = 0, imm = 0, hasSideEffects = 0, mayLoad = 0, mayStore = 0 in
375 (ins GPRNoX0:$rd, simm6nonzero:$imm),
376 "c.addi", "$rd, $imm">,
379 let Inst{6-2} = imm{4-0};
384 (ins GPRX0:$rd, immzero:$imm),
385 "c.addi", "$rd, $imm">,
401 (ins GPRNoX0:$rd, simm6:$imm),
402 "c.addiw", "$rd, $imm">,
405 let Inst{6-2} = imm{4-0};
409 def C_LI : RVInst16CI<0b010, 0b01, (outs GPRNoX0:$rd), (ins simm6:$imm),
410 "c.li", "$rd, $imm">,
412 let Inst{6-2} = imm{4-0};
417 (ins SP:$rd, simm10_lsb0000nonzero:$imm),
418 "c.addi16sp", "$rd, $imm">,
421 let Inst{12} = imm{9};
423 let Inst{6} = imm{4};
424 let Inst{5} = imm{6};
425 let Inst{4-3} = imm{8-7};
426 let Inst{2} = imm{5};
431 (ins c_lui_imm:$imm),
432 "c.lui", "$rd, $imm">,
434 let Inst{6-2} = imm{4-0};
443 def C_ANDI : RVInst16CB<0b100, 0b01, (outs GPRC:$rs1_wb), (ins GPRC:$rs1, simm6:$imm),
444 "c.andi", "$rs1, $imm">,
447 let Inst{12} = imm{5};
449 let Inst{6-2} = imm{4-0};
481 (ins GPRNoX0:$rd, uimmlog2xlennonzero:$imm),
482 "c.slli" ,"$rd, $imm">,
485 let Inst{6-2} = imm{4-0};
491 let Inst{6-5} = imm{4-3};
492 let Inst{4-2} = imm{8-6};
497 let Inst{6-4} = imm{4-2};
498 let Inst{3-2} = imm{7-6};
505 let Inst{6-4} = imm{4-2};
506 let Inst{3-2} = imm{7-6};
512 let Inst{6-5} = imm{4-3};
513 let Inst{4-2} = imm{8-6};
551 let Inst{12-10} = imm{5-3};
552 let Inst{9-7} = imm{8-6};
557 let Inst{12-9} = imm{5-2};
558 let Inst{8-7} = imm{7-6};
565 let Inst{12-9} = imm{5-2};
566 let Inst{8-7} = imm{7-6};
572 let Inst{12-10} = imm{5-3};
573 let Inst{9-7} = imm{8-6};
595 def C_NOP_HINT : RVInst16CI<0b000, 0b01, (outs), (ins simm6nonzero:$imm),
596 "c.nop", "$imm">, Sched<[WriteNop]> {
597 let Inst{6-2} = imm{4-0};
603 (ins GPRX0:$rd, simm6nonzero:$imm),
604 "c.addi", "$rd, $imm">,
607 let Inst{6-2} = imm{4-0};
612 (ins GPRNoX0:$rd, immzero:$imm),
613 "c.addi", "$rd, $imm">,
620 def C_LI_HINT : RVInst16CI<0b010, 0b01, (outs GPRX0:$rd), (ins simm6:$imm),
621 "c.li", "$rd, $imm">,
623 let Inst{6-2} = imm{4-0};
629 (ins c_lui_imm:$imm),
630 "c.lui", "$rd, $imm">,
632 let Inst{6-2} = imm{4-0};
654 (ins GPRX0:$rd, uimmlog2xlennonzero:$imm),
655 "c.slli" ,"$rd, $imm">,
658 let Inst{6-2} = imm{4-0};
759 def : CompressPat<(ADDI GPRC:$rd, SP:$rs1, uimm10_lsb00nonzero:$imm),
760 (C_ADDI4SPN GPRC:$rd, SP:$rs1, uimm10_lsb00nonzero:$imm)>;
764 def : CompressPat<(FLD FPR64C:$rd, GPRC:$rs1, uimm8_lsb000:$imm),
765 (C_FLD FPR64C:$rd, GPRC:$rs1, uimm8_lsb000:$imm)>;
769 def : CompressPat<(LW GPRC:$rd, GPRC:$rs1, uimm7_lsb00:$imm),
770 (C_LW GPRC:$rd, GPRC:$rs1, uimm7_lsb00:$imm)>;
774 def : CompressPat<(FLW FPR32C:$rd, GPRC:$rs1, uimm7_lsb00:$imm),
775 (C_FLW FPR32C:$rd, GPRC:$rs1, uimm7_lsb00:$imm)>;
779 def : CompressPat<(LD GPRC:$rd, GPRC:$rs1, uimm8_lsb000:$imm),
780 (C_LD GPRC:$rd, GPRC:$rs1, uimm8_lsb000:$imm)>;
784 def : CompressPat<(FSD FPR64C:$rs2, GPRC:$rs1, uimm8_lsb000:$imm),
785 (C_FSD FPR64C:$rs2, GPRC:$rs1, uimm8_lsb000:$imm)>;
789 def : CompressPat<(SW GPRC:$rs2, GPRC:$rs1, uimm7_lsb00:$imm),
790 (C_SW GPRC:$rs2, GPRC:$rs1, uimm7_lsb00:$imm)>;
794 def : CompressPat<(FSW FPR32C:$rs2, GPRC:$rs1,uimm7_lsb00:$imm),
795 (C_FSW FPR32C:$rs2, GPRC:$rs1, uimm7_lsb00:$imm)>;
799 def : CompressPat<(SD GPRC:$rs2, GPRC:$rs1, uimm8_lsb000:$imm),
800 (C_SD GPRC:$rs2, GPRC:$rs1, uimm8_lsb000:$imm)>;
806 def : CompressPat<(ADDI GPRNoX0:$rs1, GPRNoX0:$rs1, simm6nonzero:$imm),
807 (C_ADDI GPRNoX0:$rs1, simm6nonzero:$imm)>;
816 def : CompressPat<(ADDIW GPRNoX0:$rs1, GPRNoX0:$rs1, simm6:$imm),
817 (C_ADDIW GPRNoX0:$rs1, simm6:$imm)>;
821 def : CompressPat<(ADDI GPRNoX0:$rd, X0, simm6:$imm),
822 (C_LI GPRNoX0:$rd, simm6:$imm)>;
823 def : CompressPat<(ADDI X2, X2, simm10_lsb0000nonzero:$imm),
824 (C_ADDI16SP X2, simm10_lsb0000nonzero:$imm)>;
825 def : CompressPat<(LUI GPRNoX0X2:$rd, c_lui_imm:$imm),
826 (C_LUI GPRNoX0X2:$rd, c_lui_imm:$imm)>;
827 def : CompressPat<(SRLI GPRC:$rs1, GPRC:$rs1, uimmlog2xlennonzero:$imm),
828 (C_SRLI GPRC:$rs1, uimmlog2xlennonzero:$imm)>;
829 def : CompressPat<(SRAI GPRC:$rs1, GPRC:$rs1, uimmlog2xlennonzero:$imm),
830 (C_SRAI GPRC:$rs1, uimmlog2xlennonzero:$imm)>;
831 def : CompressPat<(ANDI GPRC:$rs1, GPRC:$rs1, simm6:$imm),
832 (C_ANDI GPRC:$rs1, simm6:$imm)>;
850 def : CompressPat<(ADDIW GPRNoX0:$rd, X0, simm6:$imm),
851 (C_LI GPRNoX0:$rd, simm6:$imm)>;
863 def : CompressPat<(BEQ GPRC:$rs1, X0, simm9_lsb0:$imm),
864 (C_BEQZ GPRC:$rs1, simm9_lsb0:$imm)>;
865 def : CompressPat<(BNE GPRC:$rs1, X0, simm9_lsb0:$imm),
866 (C_BNEZ GPRC:$rs1, simm9_lsb0:$imm)>;
871 def : CompressPat<(SLLI GPRNoX0:$rs1, GPRNoX0:$rs1, uimmlog2xlennonzero:$imm),
872 (C_SLLI GPRNoX0:$rs1, uimmlog2xlennonzero:$imm)>;
876 def : CompressPat<(FLD FPR64:$rd, SP:$rs1, uimm9_lsb000:$imm),
877 (C_FLDSP FPR64:$rd, SP:$rs1, uimm9_lsb000:$imm)>;
881 def : CompressPat<(LW GPRNoX0:$rd, SP:$rs1, uimm8_lsb00:$imm),
882 (C_LWSP GPRNoX0:$rd, SP:$rs1, uimm8_lsb00:$imm)>;
886 def : CompressPat<(FLW FPR32:$rd, SP:$rs1, uimm8_lsb00:$imm),
887 (C_FLWSP FPR32:$rd, SP:$rs1, uimm8_lsb00:$imm)>;
891 def : CompressPat<(LD GPRNoX0:$rd, SP:$rs1, uimm9_lsb000:$imm),
892 (C_LDSP GPRNoX0:$rd, SP:$rs1, uimm9_lsb000:$imm)>;
915 def : CompressPat<(FSD FPR64:$rs2, SP:$rs1, uimm9_lsb000:$imm),
916 (C_FSDSP FPR64:$rs2, SP:$rs1, uimm9_lsb000:$imm)>;
920 def : CompressPat<(SW GPR:$rs2, SP:$rs1, uimm8_lsb00:$imm),
921 (C_SWSP GPR:$rs2, SP:$rs1, uimm8_lsb00:$imm)>;
925 def : CompressPat<(FSW FPR32:$rs2, SP:$rs1, uimm8_lsb00:$imm),
926 (C_FSWSP FPR32:$rs2, SP:$rs1, uimm8_lsb00:$imm)>;
930 def : CompressPat<(SD GPR:$rs2, SP:$rs1, uimm9_lsb000:$imm),
931 (C_SDSP GPR:$rs2, SP:$rs1, uimm9_lsb000:$imm)>;