Lines Matching full:vs2
100 // load vd, (rs1), vs2, vm
104 (ins GPR:$rs1, VR:$vs2, VMaskOp:$vm), opcodestr,
105 "$vd, (${rs1}), $vs2$vm">;
130 // segment load vd, (rs1), vs2, vm
134 (ins GPR:$rs1, VR:$vs2, VMaskOp:$vm), opcodestr,
135 "$vd, (${rs1}), $vs2$vm">;
152 // store vd, vs3, (rs1), vs2, vm
155 (ins VR:$vs3, GPR:$rs1, VR:$vs2, VMaskOp:$vm),
156 opcodestr, "$vs3, (${rs1}), $vs2$vm">;
179 // segment store vd, vs3, (rs1), vs2, vm
182 (ins VR:$vs3, GPR:$rs1, VR:$vs2, VMaskOp:$vm),
183 opcodestr, "$vs3, (${rs1}), $vs2$vm">;
187 // op vd, vs2, vs1, vm
190 (ins VR:$vs2, VR:$vs1, VMaskOp:$vm),
191 opcodestr, "$vd, $vs2, $vs1$vm">;
193 // op vd, vs2, vs1, v0 (without mask, use v0 as carry input)
196 (ins VR:$vs2, VR:$vs1, VMV0:$v0),
197 opcodestr, "$vd, $vs2, $vs1, v0"> {
201 // op vd, vs1, vs2, vm (reverse the order of vs1 and vs2)
204 (ins VR:$vs1, VR:$vs2, VMaskOp:$vm),
205 opcodestr, "$vd, $vs1, $vs2$vm">;
207 // op vd, vs2, vs1
210 (ins VR:$vs2, VR:$vs1),
211 opcodestr, "$vd, $vs2, $vs1"> {
215 // op vd, vs2, rs1, vm
218 (ins VR:$vs2, GPR:$rs1, VMaskOp:$vm),
219 opcodestr, "$vd, $vs2, $rs1$vm">;
221 // op vd, vs2, rs1, v0 (without mask, use v0 as carry input)
224 (ins VR:$vs2, GPR:$rs1, VMV0:$v0),
225 opcodestr, "$vd, $vs2, $rs1, v0"> {
229 // op vd, rs1, vs2, vm (reverse the order of rs1 and vs2)
232 (ins GPR:$rs1, VR:$vs2, VMaskOp:$vm),
233 opcodestr, "$vd, $rs1, $vs2$vm">;
235 // op vd, vs1, vs2
238 (ins VR:$vs2, GPR:$rs1),
239 opcodestr, "$vd, $vs2, $rs1"> {
243 // op vd, vs2, imm, vm
246 (ins VR:$vs2, optype:$imm, VMaskOp:$vm),
247 opcodestr, "$vd, $vs2, $imm$vm">;
249 // op vd, vs2, imm, v0 (without mask, use v0 as carry input)
252 (ins VR:$vs2, optype:$imm, VMV0:$v0),
253 opcodestr, "$vd, $vs2, $imm, v0"> {
257 // op vd, vs2, imm, vm
260 (ins VR:$vs2, optype:$imm),
261 opcodestr, "$vd, $vs2, $imm"> {
265 // op vd, vs2, rs1, vm (Float)
268 (ins VR:$vs2, FPR32:$rs1, VMaskOp:$vm),
269 opcodestr, "$vd, $vs2, $rs1$vm">;
271 // op vd, rs1, vs2, vm (Float) (with mask, reverse the order of rs1 and vs2)
274 (ins FPR32:$rs1, VR:$vs2, VMaskOp:$vm),
275 opcodestr, "$vd, $rs1, $vs2$vm">;
277 // op vd, vs2, vm (use vs1 as instruction encoding)
280 (ins VR:$vs2, VMaskOp:$vm),
281 opcodestr, "$vd, $vs2$vm">;
285 // vamo vd, (rs1), vs2, vd, vm
288 (ins GPR:$rs1, VR:$vs2, VR:$vd, VMaskOp:$vm),
289 opcodestr, "$vd_wd, (${rs1}), $vs2, $vd$vm"> {
296 // vamo x0, (rs1), vs2, vs3, vm
299 (ins GPR:$rs1, VR:$vs2, VR:$vs3, VMaskOp:$vm),
300 opcodestr, "x0, (${rs1}), $vs2, $vs3$vm"> {
580 // vector register group (specified by vs2). The destination vector register
622 (ins VR:$vs2, GPR:$rs1),
623 [], "vmsgeu.vx", "$vd, $vs2, $rs1">;
625 (ins VR:$vs2, GPR:$rs1),
626 [], "vmsge.vx", "$vd, $vs2, $rs1">;
628 (ins VR:$vs2, GPR:$rs1, VMaskOp:$vm),
629 [], "vmsgeu.vx", "$vd, $vs2, $rs1$vm">;
631 (ins VR:$vs2, GPR:$rs1, VMaskOp:$vm),
632 [], "vmsge.vx", "$vd, $vs2, $rs1$vm">;
634 (ins VR:$vs2, GPR:$rs1, VMaskOp:$vm),
635 [], "vmsgeu.vx", "$vd, $vs2, $rs1$vm, $scratch">;
637 (ins VR:$vs2, GPR:$rs1, VMaskOp:$vm),
638 [], "vmsge.vx", "$vd, $vs2, $rs1$vm, $scratch">;
641 // This apparently unnecessary alias prevents matching `vmsge{u}.vx vd, vs2, vs1` as if
703 let hasSideEffects = 0, mayLoad = 0, mayStore = 0, vs2 = 0, vm = 1 in {
822 (ins VR:$vs2, FPR32:$rs1, VMV0:$v0),
823 "vfmerge.vfm", "$vd, $vs2, $rs1, v0"> {
830 let vs2 = 0;
928 (ins VR:$vs2, VMaskOp:$vm),
929 "vpopc.m", "$vd, $vs2$vm">;
933 (ins VR:$vs2, VMaskOp:$vm),
934 "vfirst.m", "$vd, $vs2$vm">;
955 let vs2 = 0;
961 (ins VR:$vs2), "vmv.x.s", "$vd, $vs2">;
971 (ins VR:$vs2), "vfmv.f.s", "$vd, $vs2">;
1003 (ins VR:$vs2), "vmv" # nf # "r.v",
1004 "$vd, $vs2"> {