Lines Matching refs:rd
14 // mov<cond> <ccreg> rs2, rd
19 // mov<cond> (%icc|%xcc), rs2, rd
21 ", $rs2, $rd"),
22 (movrr IntRegs:$rd, IntRegs:$rs2, condVal)>;
24 // mov<cond> (%icc|%xcc), simm11, rd
26 ", $simm11, $rd"),
27 (movri IntRegs:$rd, i32imm:$simm11, condVal)>;
29 // fmovs<cond> (%icc|%xcc), $rs2, $rd
31 ", $rs2, $rd"),
32 (fmovs FPRegs:$rd, FPRegs:$rs2, condVal)>;
34 // fmovd<cond> (%icc|%xcc), $rs2, $rd
36 ", $rs2, $rd"),
37 (fmovd DFPRegs:$rd, DFPRegs:$rs2, condVal)>;
40 // mov<cond> <ccreg> rs2, rd
45 // mov<cond> %fcc[0-3], rs2, rd
46 def : InstAlias<!strconcat(!strconcat("mov", cond), " $cc, $rs2, $rd"),
47 (movrr IntRegs:$rd, FCCRegs:$cc, IntRegs:$rs2, condVal)>;
49 // mov<cond> %fcc[0-3], simm11, rd
50 def : InstAlias<!strconcat(!strconcat("mov", cond), " $cc, $simm11, $rd"),
51 (movri IntRegs:$rd, FCCRegs:$cc, i32imm:$simm11, condVal)>;
53 // fmovs<cond> %fcc[0-3], $rs2, $rd
54 def : InstAlias<!strconcat(!strconcat("fmovs", cond), " $cc, $rs2, $rd"),
55 (fmovs FPRegs:$rd, FCCRegs:$cc, FPRegs:$rs2, condVal)>;
57 // fmovd<cond> %fcc[0-3], $rs2, $rd
58 def : InstAlias<!strconcat(!strconcat("fmovd", cond), " $cc, $rs2, $rd"),
59 (fmovd DFPRegs:$rd, FCCRegs:$cc, DFPRegs:$rs2, condVal)>;
130 // fmovq<cond> (%icc|%xcc), $rs2, $rd
131 def : InstAlias<!strconcat(!strconcat("fmovq", cond), " %icc, $rs2, $rd"),
132 (FMOVQ_ICC QFPRegs:$rd, QFPRegs:$rs2, condVal)>,
134 def : InstAlias<!strconcat(!strconcat("fmovq", cond), " %xcc, $rs2, $rd"),
135 (FMOVQ_XCC QFPRegs:$rd, QFPRegs:$rs2, condVal)>,
248 // fmovq<cond> %fcc0, $rs2, $rd
249 def : InstAlias<!strconcat(!strconcat("fmovq", cond), " $cc, $rs2, $rd"),
250 (V9FMOVQ_FCC QFPRegs:$rd, FCCRegs:$cc, QFPRegs:$rs2,
368 // set value, rd
370 // def : InstAlias<"set $val, $rd", (ORri IntRegs:$rd, (SETHIi (HI22 imm:$val)), (LO10 imm:$val))>;
371 def SET : AsmPseudoInst<(outs IntRegs:$rd), (ins i32imm:$val), "set $val, $rd">;
373 // not rd -> xnor rd, %g0, rd
374 def : InstAlias<"not $rd", (XNORrr IntRegs:$rd, IntRegs:$rd, G0), 0>;
376 // not reg, rd -> xnor reg, %g0, rd
377 def : InstAlias<"not $rs1, $rd", (XNORrr IntRegs:$rd, IntRegs:$rs1, G0), 0>;
379 // neg rd -> sub %g0, rd, rd
380 def : InstAlias<"neg $rd", (SUBrr IntRegs:$rd, G0, IntRegs:$rd), 0>;
382 // neg reg, rd -> sub %g0, reg, rd
383 def : InstAlias<"neg $rs2, $rd", (SUBrr IntRegs:$rd, G0, IntRegs:$rs2), 0>;
385 // inc rd -> add rd, 1, rd
386 def : InstAlias<"inc $rd", (ADDri IntRegs:$rd, IntRegs:$rd, 1), 0>;
388 // inc simm13, rd -> add rd, simm13, rd
389 def : InstAlias<"inc $simm13, $rd", (ADDri IntRegs:$rd, IntRegs:$rd, i32imm:$simm13), 0>;
391 // inccc rd -> addcc rd, 1, rd
392 def : InstAlias<"inccc $rd", (ADDCCri IntRegs:$rd, IntRegs:$rd, 1), 0>;
394 // inccc simm13, rd -> addcc rd, simm13, rd
395 def : InstAlias<"inccc $simm13, $rd", (ADDCCri IntRegs:$rd, IntRegs:$rd, i32imm:$simm13), 0>;
397 // dec rd -> sub rd, 1, rd
398 def : InstAlias<"dec $rd", (SUBri IntRegs:$rd, IntRegs:$rd, 1), 0>;
400 // dec simm13, rd -> sub rd, simm13, rd
401 def : InstAlias<"dec $simm13, $rd", (SUBri IntRegs:$rd, IntRegs:$rd, i32imm:$simm13), 0>;
403 // deccc rd -> subcc rd, 1, rd
404 def : InstAlias<"deccc $rd", (SUBCCri IntRegs:$rd, IntRegs:$rd, 1), 0>;
406 // deccc simm13, rd -> subcc rd, simm13, rd
407 def : InstAlias<"deccc $simm13, $rd", (SUBCCri IntRegs:$rd, IntRegs:$rd, i32imm:$simm13), 0>;
413 // bset reg_or_imm, rd -> or rd,reg_or_imm,rd
414 def : InstAlias<"bset $rs2, $rd", (ORrr IntRegs:$rd, IntRegs:$rd, IntRegs:$rs2), 0>;
415 def : InstAlias<"bset $simm13, $rd", (ORri IntRegs:$rd, IntRegs:$rd, i32imm:$simm13), 0>;
417 // bclr reg_or_imm, rd -> andn rd,reg_or_imm,rd
418 def : InstAlias<"bclr $rs2, $rd", (ANDNrr IntRegs:$rd, IntRegs:$rd, IntRegs:$rs2), 0>;
419 def : InstAlias<"bclr $simm13, $rd", (ANDNri IntRegs:$rd, IntRegs:$rd, i32imm:$simm13), 0>;
421 // btog reg_or_imm, rd -> xor rd,reg_or_imm,rd
422 def : InstAlias<"btog $rs2, $rd", (XORrr IntRegs:$rd, IntRegs:$rd, IntRegs:$rs2), 0>;
423 def : InstAlias<"btog $simm13, $rd", (XORri IntRegs:$rd, IntRegs:$rd, i32imm:$simm13), 0>;
426 // clr rd -> or %g0, %g0, rd
427 def : InstAlias<"clr $rd", (ORrr IntRegs:$rd, G0, G0), 0>;
438 // mov reg_or_imm, rd -> or %g0, reg_or_imm, rd
439 def : InstAlias<"mov $rs2, $rd", (ORrr IntRegs:$rd, G0, IntRegs:$rs2)>;
440 def : InstAlias<"mov $simm13, $rd", (ORri IntRegs:$rd, G0, i32imm:$simm13)>;
442 // mov specialreg, rd -> rd specialreg, rd
443 def : InstAlias<"mov $asr, $rd", (RDASR IntRegs:$rd, ASRRegs:$asr), 0>;
444 def : InstAlias<"mov %psr, $rd", (RDPSR IntRegs:$rd), 0>;
445 def : InstAlias<"mov %wim, $rd", (RDWIM IntRegs:$rd), 0>;
446 def : InstAlias<"mov %tbr, $rd", (RDTBR IntRegs:$rd), 0>;
519 // signx rd -> sra rd, %g0, rd
520 def : InstAlias<"signx $rd", (SRArr IntRegs:$rd, IntRegs:$rd, G0), 0>, Requires<[HasV9]>;
522 // signx reg, rd -> sra reg, %g0, rd
523 def : InstAlias<"signx $rs1, $rd", (SRArr IntRegs:$rd, IntRegs:$rs1, G0), 0>, Requires<[HasV9]>;