Lines Matching refs:RegKind
116 unsigned RegKind : 4; member
182 createMem(MemoryKind MemKind, RegisterKind RegKind, unsigned Base, in createMem() argument
187 Op->Mem.RegKind = RegKind; in createMem()
220 bool isReg(RegisterKind RegKind) const { in isReg()
221 return Kind == KindReg && Reg.Kind == RegKind; in isReg()
261 bool isMem(MemoryKind MemKind, RegisterKind RegKind) const { in isMem()
262 return isMem(MemKind) && Mem.RegKind == RegKind; in isMem()
264 bool isMemDisp12(MemoryKind MemKind, RegisterKind RegKind) const { in isMemDisp12()
265 return isMem(MemKind, RegKind) && inRange(Mem.Disp, 0, 0xfff); in isMemDisp12()
267 bool isMemDisp20(MemoryKind MemKind, RegisterKind RegKind) const { in isMemDisp20()
268 return isMem(MemKind, RegKind) && inRange(Mem.Disp, -524288, 524287); in isMemDisp20()
270 bool isMemDisp12Len4(RegisterKind RegKind) const { in isMemDisp12Len4()
271 return isMemDisp12(BDLMem, RegKind) && inRange(Mem.Length.Imm, 1, 0x10); in isMemDisp12Len4()
273 bool isMemDisp12Len8(RegisterKind RegKind) const { in isMemDisp12Len8()
274 return isMemDisp12(BDLMem, RegKind) && inRange(Mem.Length.Imm, 1, 0x100); in isMemDisp12Len8()
424 RegisterKind RegKind);
1056 RegisterKind RegKind) { in parseAddress() argument
1071 switch (RegKind) { in parseAddress()
1160 Operands.push_back(SystemZOperand::createMem(MemKind, RegKind, Base, Disp, in parseAddress()