Lines Matching refs:cls2
2792 RegisterOperand cls1, RegisterOperand cls2>
2793 : InstRR<opcode, (outs cls1:$R1), (ins cls2:$R2),
2795 [(set cls1:$R1, (operator cls2:$R2))]> {
2801 RegisterOperand cls1, RegisterOperand cls2>
2802 : InstRRE<opcode, (outs cls1:$R1), (ins cls2:$R2),
2804 [(set cls1:$R1, (operator cls2:$R2))]> {
2818 RegisterOperand cls1, RegisterOperand cls2>
2819 : InstRRFc<opcode, (outs cls2:$R2, cls1:$R1), (ins cls1:$R1src),
3073 RegisterOperand cls1, RegisterOperand cls2>
3074 : InstRRE<opcode, (outs), (ins cls1:$R1, cls2:$R2),
3078 RegisterOperand cls1, RegisterOperand cls2>
3079 : InstRRFa<opcode, (outs), (ins cls1:$R1, cls2:$R2),
3086 RegisterOperand cls1, RegisterOperand cls2>
3087 : InstRRFc<opcode, (outs), (ins cls1:$R1, cls2:$R2),
3124 RegisterOperand cls1, RegisterOperand cls2>
3125 : InstRR<opcode, (outs cls1:$R1, cls2:$R2), (ins cls1:$R1src, cls2:$R2src),
3132 RegisterOperand cls1, RegisterOperand cls2>
3133 : InstRRE<opcode, (outs cls2:$R2), (ins cls1:$R1, cls2:$R2src),
3140 RegisterOperand cls1, RegisterOperand cls2>
3141 : InstRRE<opcode, (outs cls1:$R1, cls2:$R2), (ins cls1:$R1src, cls2:$R2src),
3148 RegisterOperand cls1, RegisterOperand cls2>
3149 : InstRRFc<opcode, (outs cls1:$R1, cls2:$R2), (ins cls1:$R1src, cls2:$R2src),
3157 RegisterOperand cls1, RegisterOperand cls2>
3158 : InstRR<opcode, (outs cls1:$R1), (ins cls1:$R1src, cls2:$R2),
3160 [(set cls1:$R1, (operator cls1:$R1src, cls2:$R2))]> {
3168 RegisterOperand cls1, RegisterOperand cls2>
3169 : InstRRE<opcode, (outs cls1:$R1), (ins cls1:$R1src, cls2:$R2),
3171 [(set cls1:$R1, (operator cls1:$R1src, cls2:$R2))]> {
3179 RegisterOperand cls1, RegisterOperand cls2>
3180 : InstRRD<opcode, (outs cls1:$R1), (ins cls2:$R3, cls2:$R2),
3182 [(set cls1:$R1, (operator cls2:$R3, cls2:$R2))]> {
3188 RegisterOperand cls1, RegisterOperand cls2,
3190 : InstRRFa<opcode, (outs cls1:$R1), (ins cls2:$R2, cls3:$R3),
3192 [(set cls1:$R1, (operator cls2:$R2, cls3:$R3))]> {
3200 RegisterOperand cls2> {
3203 def K : BinaryRRFa<mnemonic#"k", opcode2, operator, cls1, cls1, cls2>,
3206 def "" : BinaryRR<mnemonic, opcode1, operator, cls1, cls2>;
3212 RegisterOperand cls2> {
3215 def K : BinaryRRFa<mnemonic#"k", opcode2, operator, cls1, cls1, cls2>,
3218 def "" : BinaryRRE<mnemonic, opcode1, operator, cls1, cls2>;
3223 RegisterOperand cls1, RegisterOperand cls2,
3225 : InstRRFb<opcode, (outs cls1:$R1), (ins cls2:$R2, cls3:$R3),
3227 [(set cls1:$R1, (operator cls2:$R2, cls3:$R3))]> {
3232 RegisterOperand cls1, RegisterOperand cls2>
3233 : InstRRFc<opcode, (outs cls1:$R1), (ins cls2:$R2, imm32zx4:$M3),
3237 RegisterOperand cls1, RegisterOperand cls2, ImmOpWithPattern imm>
3238 : InstRRFc<opcode, (outs cls2:$R2, cls1:$R1), (ins cls1:$R1src, imm:$M3),
3245 RegisterOperand cls1, RegisterOperand cls2> {
3246 def "" : BinaryMemRRFc<mnemonic, opcode, cls1, cls2, imm32zx4>;
3247 def Opt : UnaryMemRRFc<mnemonic, opcode, cls1, cls2>;
3251 RegisterOperand cls2>
3252 : InstRRFd<opcode, (outs cls1:$R1), (ins cls2:$R2, imm32zx4:$M4),
3256 RegisterOperand cls2>
3257 : InstRRFe<opcode, (outs cls1:$R1), (ins imm32zx4:$M3, cls2:$R2),
3263 RegisterOperand cls2>
3265 (ins cls1:$R1src, cls2:$R2, cond4:$valid, cond4:$M3),
3267 [(set cls1:$R1, (z_select_ccmask cls2:$R2, cls1:$R1src,
3281 RegisterOperand cls2>
3283 (ins cls1:$R1src, cls2:$R2, imm32zx4:$M3),
3291 RegisterOperand cls1, RegisterOperand cls2>
3292 : InstRRFc<opcode, (outs cls1:$R1), (ins cls1:$R1src, cls2:$R2),
3301 RegisterOperand cls1, RegisterOperand cls2> {
3303 def "" : CondBinaryRRF<mnemonic, opcode, cls1, cls2>;
3304 def Asm : AsmCondBinaryRRF<mnemonic, opcode, cls1, cls2>;
3308 RegisterOperand cls2, RegisterOperand cls3>
3310 (ins cls3:$R3, cls2:$R2, cond4:$valid, cond4:$M4),
3312 [(set cls1:$R1, (z_select_ccmask cls2:$R2, cls3:$R3,
3324 RegisterOperand cls2, RegisterOperand cls3>
3325 : InstRRFa<opcode, (outs cls1:$R1), (ins cls3:$R3, cls2:$R2, imm32zx4:$M4),
3330 RegisterOperand cls1, RegisterOperand cls2,
3332 : InstRRFa<opcode, (outs cls1:$R1), (ins cls3:$R3, cls2:$R2),
3339 RegisterOperand cls1, RegisterOperand cls2,
3342 def "" : CondBinaryRRFa<mnemonic, opcode, cls1, cls2, cls3>;
3343 def Asm : AsmCondBinaryRRFa<mnemonic, opcode, cls1, cls2, cls3>;
3487 RegisterOperand cls1, RegisterOperand cls2,
3489 : InstRXF<opcode, (outs cls1:$R1), (ins cls2:$R3, bdxaddr12only:$XBD2),
3491 [(set cls1:$R1, (operator cls2:$R3, (load bdxaddr12only:$XBD2)))]> {
3871 RegisterOperand cls1, RegisterOperand cls2>
3872 : InstRR<opcode, (outs), (ins cls1:$R1, cls2:$R2),
3874 [(set CC, (operator cls1:$R1, cls2:$R2))]> {
3881 RegisterOperand cls1, RegisterOperand cls2>
3882 : InstRRE<opcode, (outs), (ins cls1:$R1, cls2:$R2),
3884 [(set CC, (operator cls1:$R1, cls2:$R2))]> {
4117 RegisterOperand cls1, RegisterOperand cls2,
4119 : InstRRFa<opcode, (outs), (ins cls1:$R1, cls2:$R2, cls3:$R3),
4125 RegisterOperand cls1, RegisterOperand cls2,
4127 : InstRRFa<opcode, (outs cls1:$R1, cls2:$R2),
4128 (ins cls1:$R1src, cls2:$R2src, cls3:$R3),
4136 RegisterOperand cls1, RegisterOperand cls2,
4138 : InstRRFb<opcode, (outs), (ins cls1:$R1, cls2:$R2, cls3:$R3),
4145 RegisterOperand cls2,
4147 : InstRRFb<opcode, (outs cls1:$R1, cls2:$R2, cls3:$R3),
4148 (ins cls1:$R1src, cls2:$R2src, cls3:$R3src),
4156 RegisterOperand cls1, RegisterOperand cls2,
4158 : InstRRFc<opcode, (outs), (ins cls1:$R1, cls2:$R2, imm:$M3),
4163 RegisterOperand cls2> {
4164 def "" : SideEffectTernaryRRFc<mnemonic, opcode, cls1, cls2, imm32zx4>;
4165 def Opt : SideEffectBinaryRRFc<mnemonic, opcode, cls1, cls2>;
4169 RegisterOperand cls1, RegisterOperand cls2,
4171 : InstRRFc<opcode, (outs cls1:$R1, cls2:$R2),
4172 (ins cls1:$R1src, cls2:$R2src, imm:$M3),
4180 RegisterOperand cls2> {
4181 def "" : SideEffectTernaryMemMemRRFc<mnemonic, opcode, cls1, cls2, imm32zx4>;
4182 def Opt : SideEffectBinaryMemMemRRFc<mnemonic, opcode, cls1, cls2>;
4192 RegisterOperand cls1, RegisterOperand cls2,
4194 : InstRRFa<opcode, (outs cls1:$R1), (ins cls2:$R2, cls3:$R3, imm32zx4:$M4),
4198 RegisterOperand cls1, RegisterOperand cls2,
4201 (ins cls1:$R1src, cls2:$R2, imm32zx4:$M4),
4208 RegisterOperand cls2>
4210 (ins imm32zx4:$M3, cls2:$R2, imm32zx4:$M4),
4214 RegisterOperand cls1, RegisterOperand cls2>
4215 : InstRRD<opcode, (outs cls1:$R1), (ins cls2:$R1src, cls2:$R3, cls2:$R2),
4217 [(set cls1:$R1, (operator cls2:$R1src, cls2:$R3, cls2:$R2))]> {
4259 RegisterOperand cls1, RegisterOperand cls2>
4261 (ins cls1:$R1, cls2:$R3, bdaddr12only:$BD2),
4265 RegisterOperand cls1, RegisterOperand cls2>
4267 (ins cls1:$R1, cls2:$R3, bdaddr20only:$BD2),
4271 RegisterOperand cls1, RegisterOperand cls2>
4272 : InstRSa<opcode, (outs cls1:$R1, cls2:$R3),
4273 (ins cls1:$R1src, cls2:$R3src, shift12only:$BD2),
4280 RegisterOperand cls1, RegisterOperand cls2>
4281 : InstRSYa<opcode, (outs cls1:$R1, cls2:$R3),
4282 (ins cls1:$R1src, cls2:$R3src, shift20only:$BD2),
4289 RegisterOperand cls1, RegisterOperand cls2,
4292 (ins cls2:$R1src, cls2:$R3, bdxaddr12only:$XBD2),
4294 [(set cls1:$R1, (operator cls2:$R1src, cls2:$R3,
4627 RegisterOperand cls1, RegisterOperand cls2,
4629 : InstRRFa<opcode, (outs), (ins cls1:$R1, cls2:$R2, cls3:$R3, imm32zx4:$M4),
4634 RegisterOperand cls2,
4636 def "" : SideEffectQuaternaryRRFa<mnemonic, opcode, cls1, cls2, cls3>;
4637 def Opt : SideEffectTernaryRRFa<mnemonic, opcode, cls1, cls2, cls3>;
4638 def OptOpt : SideEffectBinaryRRFa<mnemonic, opcode, cls1, cls2>;
4642 RegisterOperand cls1, RegisterOperand cls2,
4644 : InstRRFb<opcode, (outs), (ins cls1:$R1, cls2:$R2, cls3:$R3, imm32zx4:$M4),
4649 RegisterOperand cls2,
4651 def "" : SideEffectQuaternaryRRFb<mnemonic, opcode, cls1, cls2, cls3>;
4652 def Opt : SideEffectTernaryRRFb<mnemonic, opcode, cls1, cls2, cls3>;
4671 RegisterOperand cls1, RegisterOperand cls2>
4672 : InstRRE<opcode, (outs cls1:$R1), (ins cls1:$R1src, cls2:$R2),
4713 RegisterOperand cls2>
4715 (ins cls1:$R1src, cls2:$R2, imm32zx8:$I3, imm32zx8:$I4,
4798 RegisterOperand cls1, RegisterOperand cls2>
4799 : Pseudo<(outs cls1:$R1), (ins cls2:$R2),
4800 [(set cls1:$R1, (operator cls2:$R2))]> {
4913 RegisterOperand cls2>
4915 (ins cls1:$R1src, cls2:$R2, cond4:$valid, cond4:$M3),
4916 [(set cls1:$R1, (z_select_ccmask cls2:$R2, cls1:$R1src,
4930 RegisterOperand cls2, RegisterOperand cls3>
4932 (ins cls3:$R3, cls2:$R2, cond4:$valid, cond4:$M4),
4933 [(set cls1:$R1, (z_select_ccmask cls2:$R2, cls3:$R3,
4998 class RotateSelectRIEfPseudo<RegisterOperand cls1, RegisterOperand cls2>
5000 (ins cls1:$R1src, cls2:$R2, imm32zx8:$I3, imm32zx8:$I4,
5094 class UnaryAliasVRS<RegisterOperand cls1, RegisterOperand cls2>
5095 : Alias<6, (outs cls1:$src1), (ins cls2:$src2), []>;
5143 class RotateSelectAliasRIEf<RegisterOperand cls1, RegisterOperand cls2>
5145 (ins cls1:$R1src, cls2:$R2, imm32zx8:$I3, imm32zx8:$I4,
5196 RegisterOperand cls2, SDPatternOperator load,
5198 def "" : TernaryRXF<mnemonic, opcode, operator, cls1, cls2, load, bytes> {