Lines Matching refs:vec_t
59 foreach vec_t = [v16i8, v8i16, v4i32, v2i64, v4f32, v2f64] in {
60 defm : LoadPatNoOffset<vec_t, load, "LOAD_V128">;
61 defm : LoadPatImmOff<vec_t, load, regPlusImm, "LOAD_V128">;
62 defm : LoadPatImmOff<vec_t, load, or_is_add, "LOAD_V128">;
63 defm : LoadPatOffsetOnly<vec_t, load, "LOAD_V128">;
64 defm : LoadPatGlobalAddrOffOnly<vec_t, load, "LOAD_V128">;
119 multiclass SIMDLoadExtend<ValueType vec_t, string name, bits<32> simdop> {
121 defm LOAD_EXTEND_S_#vec_t#_A32 :
127 defm LOAD_EXTEND_U_#vec_t#_A32 :
133 defm LOAD_EXTEND_S_#vec_t#_A64 :
139 defm LOAD_EXTEND_U_#vec_t#_A64 :
169 multiclass SIMDLoadZero<ValueType vec_t, string name, bits<32> simdop> {
171 defm LOAD_ZERO_#vec_t#_A32 :
177 defm LOAD_ZERO_#vec_t#_A64 :
207 multiclass SIMDLoadLane<ValueType vec_t, string name, bits<32> simdop> {
209 defm LOAD_LANE_#vec_t#_A32 :
216 defm LOAD_LANE_#vec_t#_A64 :
266 foreach vec_t = [v16i8, v8i16, v4i32, v2i64, v4f32, v2f64] in {
267 defm : StorePatNoOffset<vec_t, store, "STORE_V128">;
268 defm : StorePatImmOff<vec_t, store, regPlusImm, "STORE_V128">;
269 defm : StorePatImmOff<vec_t, store, or_is_add, "STORE_V128">;
270 defm : StorePatOffsetOnly<vec_t, store, "STORE_V128">;
271 defm : StorePatGlobalAddrOffOnly<vec_t, store, "STORE_V128">;
275 multiclass SIMDStoreLane<ValueType vec_t, string name, bits<32> simdop> {
277 defm STORE_LANE_#vec_t#_A32 :
284 defm STORE_LANE_#vec_t#_A64 :
326 multiclass ConstVec<ValueType vec_t, dag ops, dag pat, string args> {
329 defm CONST_V128_#vec_t : SIMD_I<(outs V128:$dst), ops, (outs), ops,
330 [(set V128:$dst, (vec_t pat))],
415 foreach vec_t = [v16i8, v8i16, v4i32, v2i64, v4f32, v2f64] in {
416 def : Pat<(vec_t (wasm_shuffle (vec_t V128:$x), (vec_t V128:$y),
425 (vec_t (SHUFFLE (vec_t V128:$x), (vec_t V128:$y),
461 multiclass Splat<ValueType vec_t, string vec, WebAssemblyRegClass reg_t,
463 defm SPLAT_#vec_t : SIMD_I<(outs V128:$dst), (ins reg_t:$x), (outs), (ins),
464 [(set (vec_t V128:$dst), (splat_pat reg_t:$x))],
476 class ScalarSplatPat<ValueType vec_t, ValueType lane_t,
478 Pat<(vec_t (scalar_to_vector (lane_t reg_t:$x))),
479 (!cast<Instruction>("SPLAT_"#vec_t) reg_t:$x)>;
493 multiclass ExtractLane<ValueType vec_t, string vec, WebAssemblyRegClass reg_t,
495 defm EXTRACT_LANE_#vec_t#suffix :
538 multiclass ReplaceLane<ValueType vec_t, string vec, ImmLeaf imm_t,
541 defm REPLACE_LANE_#vec_t :
545 (vec_t V128:$vec), (lane_t reg_t:$x), (i32 imm_t:$idx)))],
575 multiclass SIMDCondition<ValueType vec_t, ValueType out_t, string vec,
577 defm _#vec_t :
580 (setcc (vec_t V128:$lhs), (vec_t V128:$rhs), cond)
657 multiclass SIMDBinary<ValueType vec_t, string vec, SDNode node, string name,
659 defm _#vec_t : SIMD_I<(outs V128:$dst), (ins V128:$lhs, V128:$rhs),
661 [(set (vec_t V128:$dst),
662 (node (vec_t V128:$lhs), (vec_t V128:$rhs))
675 multiclass SIMDUnary<ValueType vec_t, string vec, SDNode node, string name,
677 defm _#vec_t : SIMD_I<(outs V128:$dst), (ins V128:$vec), (outs), (ins),
678 [(set (vec_t V128:$dst),
679 (vec_t (node (vec_t V128:$vec)))
685 foreach vec_t = [v16i8, v8i16, v4i32, v2i64] in
686 defm NOT: SIMDUnary<vec_t, "v128", vnot, "not", 77>;
700 foreach vec_t = [v16i8, v8i16, v4i32, v2i64, v4f32, v2f64] in
701 defm BITSELECT_#vec_t :
703 [(set (vec_t V128:$dst),
704 (vec_t (int_wasm_bitselect
705 (vec_t V128:$v1), (vec_t V128:$v2), (vec_t V128:$c)
711 foreach vec_t = [v16i8, v8i16, v4i32, v2i64] in
712 def : Pat<(vec_t (or (and (vec_t V128:$c), (vec_t V128:$v1)),
713 (and (vnot V128:$c), (vec_t V128:$v2)))),
714 (!cast<Instruction>("BITSELECT_"#vec_t)
728 foreach vec_t = [v16i8, v8i16, v4i32, v2i64, v4f32, v2f64] in {
729 defm SELECT_#vec_t : I<(outs V128:$dst), (ins V128:$lhs, V128:$rhs, I32:$cond),
733 (vec_t V128:$lhs), (vec_t V128:$rhs)
743 (i32 (setne I32:$cond, 0)), (vec_t V128:$lhs), (vec_t V128:$rhs)
745 (!cast<Instruction>("SELECT_"#vec_t)
751 (i32 (seteq I32:$cond, 0)), (vec_t V128:$lhs), (vec_t V128:$rhs)
753 (!cast<Instruction>("SELECT_"#vec_t)
756 } // foreach vec_t
759 multiclass SIMDSignSelect<ValueType vec_t, string vec, bits<32> simdop> {
760 defm SIGNSELECT_#vec_t :
762 [(set (vec_t V128:$dst),
763 (vec_t (int_wasm_signselect
764 (vec_t V128:$v1), (vec_t V128:$v2), (vec_t V128:$c)
786 multiclass SIMDReduceVec<ValueType vec_t, string vec, SDNode op, string name,
788 defm _#vec_t : SIMD_I<(outs I32:$dst), (ins V128:$vec), (outs), (ins),
789 [(set I32:$dst, (i32 (op (vec_t V128:$vec))))],
840 multiclass SIMDBitmask<ValueType vec_t, string vec, bits<32> simdop> {
841 defm _#vec_t : SIMD_I<(outs I32:$dst), (ins V128:$vec), (outs), (ins),
843 (i32 (int_wasm_bitmask (vec_t V128:$vec)))
857 multiclass SIMDShift<ValueType vec_t, string vec, SDNode node, string name,
859 defm _#vec_t : SIMD_I<(outs V128:$dst), (ins V128:$vec, I32:$x),
861 [(set (vec_t V128:$dst), (node V128:$vec, I32:$x))],
967 multiclass SIMDExtBinary<ValueType vec_t, ValueType arg_t, string vec,
969 defm _#vec_t : SIMD_I<(outs V128:$dst), (ins V128:$lhs, V128:$rhs),
971 [(set (vec_t V128:$dst),
1084 multiclass SIMDConvert<ValueType vec_t, ValueType arg_t, SDNode op,
1086 defm op#_#vec_t#_#arg_t :
1088 [(set (vec_t V128:$dst), (vec_t (op (arg_t V128:$vec))))],
1113 multiclass SIMDWiden<ValueType vec_t, string vec, ValueType arg_t, string arg,
1115 defm "" : SIMDConvert<vec_t, arg_t, widen_low_s,
1117 defm "" : SIMDConvert<vec_t, arg_t, widen_high_s,
1119 defm "" : SIMDConvert<vec_t, arg_t, widen_low_u,
1121 defm "" : SIMDConvert<vec_t, arg_t, widen_high_u,
1138 multiclass SIMDNarrow<ValueType vec_t, string vec, ValueType arg_t, string arg,
1140 defm NARROW_S_#vec_t :
1142 [(set (vec_t V128:$dst), (vec_t (int_wasm_narrow_signed
1146 defm NARROW_U_#vec_t :
1148 [(set (vec_t V128:$dst), (vec_t (int_wasm_narrow_unsigned
1262 multiclass SIMDQFM<ValueType vec_t, string vec, bits<32> simdopA,
1264 defm QFMA_#vec_t :
1267 [(set (vec_t V128:$dst),
1268 (int_wasm_qfma (vec_t V128:$a), (vec_t V128:$b), (vec_t V128:$c)))],
1270 defm QFMS_#vec_t :
1273 [(set (vec_t V128:$dst),
1274 (int_wasm_qfms (vec_t V128:$a), (vec_t V128:$b), (vec_t V128:$c)))],