426     unsigned BaseReg, IndexReg, TmpReg, Scale;  member in __anona5c84dc30111::X86AsmParser::IntelExprStateMachine
450         : State(IES_INIT), PrevState(IES_ERROR), BaseReg(0), IndexReg(0),  in IntelExprStateMachine()
460     unsigned getIndexReg() const { return IndexReg; }  in getIndexReg()
658             if (IndexReg) {  in onPlus()
662             IndexReg = TmpReg;  in onPlus()
719             if (IndexReg) {  in onMinus()
723             IndexReg = TmpReg;  in onMinus()
780           if (IndexReg) {  in onRegister()
785           IndexReg = Reg;  in onRegister()
864           if (IndexReg) {  in onInteger()
868           IndexReg = TmpReg;  in onInteger()
967             assert (!IndexReg && "BaseReg/IndexReg already set!");  in onRBrac()
968             IndexReg = TmpReg;  in onRBrac()
1122                                unsigned BaseReg, unsigned IndexReg,
1274 static bool CheckBaseRegAndIndexRegAndScale(unsigned BaseReg, unsigned IndexReg,  in CheckBaseRegAndIndexRegAndScale()  argument
1290   if (IndexReg != 0 &&  in CheckBaseRegAndIndexRegAndScale()
1291       !(IndexReg == X86::EIZ || IndexReg == X86::RIZ ||  in CheckBaseRegAndIndexRegAndScale()
1292         X86MCRegisterClasses[X86::GR16RegClassID].contains(IndexReg) ||  in CheckBaseRegAndIndexRegAndScale()
1293         X86MCRegisterClasses[X86::GR32RegClassID].contains(IndexReg) ||  in CheckBaseRegAndIndexRegAndScale()
1294         X86MCRegisterClasses[X86::GR64RegClassID].contains(IndexReg) ||  in CheckBaseRegAndIndexRegAndScale()
1295         X86MCRegisterClasses[X86::VR128XRegClassID].contains(IndexReg) ||  in CheckBaseRegAndIndexRegAndScale()
1296         X86MCRegisterClasses[X86::VR256XRegClassID].contains(IndexReg) ||  in CheckBaseRegAndIndexRegAndScale()
1297         X86MCRegisterClasses[X86::VR512RegClassID].contains(IndexReg))) {  in CheckBaseRegAndIndexRegAndScale()
1302   if (((BaseReg == X86::RIP || BaseReg == X86::EIP) && IndexReg != 0) ||  in CheckBaseRegAndIndexRegAndScale()
1303       IndexReg == X86::EIP || IndexReg == X86::RIP ||  in CheckBaseRegAndIndexRegAndScale()
1304       IndexReg == X86::ESP || IndexReg == X86::RSP) {  in CheckBaseRegAndIndexRegAndScale()
1319       X86MCRegisterClasses[X86::GR16RegClassID].contains(IndexReg)) {  in CheckBaseRegAndIndexRegAndScale()
1324   if (BaseReg != 0 && IndexReg != 0) {  in CheckBaseRegAndIndexRegAndScale()
1326         (X86MCRegisterClasses[X86::GR16RegClassID].contains(IndexReg) ||  in CheckBaseRegAndIndexRegAndScale()
1327          X86MCRegisterClasses[X86::GR32RegClassID].contains(IndexReg) ||  in CheckBaseRegAndIndexRegAndScale()
1328          IndexReg == X86::EIZ)) {  in CheckBaseRegAndIndexRegAndScale()
1333         (X86MCRegisterClasses[X86::GR16RegClassID].contains(IndexReg) ||  in CheckBaseRegAndIndexRegAndScale()
1334          X86MCRegisterClasses[X86::GR64RegClassID].contains(IndexReg) ||  in CheckBaseRegAndIndexRegAndScale()
1335          IndexReg == X86::RIZ)) {  in CheckBaseRegAndIndexRegAndScale()
1340       if (X86MCRegisterClasses[X86::GR32RegClassID].contains(IndexReg) ||  in CheckBaseRegAndIndexRegAndScale()
1341           X86MCRegisterClasses[X86::GR64RegClassID].contains(IndexReg)) {  in CheckBaseRegAndIndexRegAndScale()
1346           (IndexReg != X86::SI && IndexReg != X86::DI)) {  in CheckBaseRegAndIndexRegAndScale()
1727     unsigned SegReg, const MCExpr *Disp, unsigned BaseReg, unsigned IndexReg,  in CreateMemForMSInlineAsm()  argument
1760   if (IsGlobalLV && (BaseReg || IndexReg)) {  in CreateMemForMSInlineAsm()
1770       getPointerWidth(), SegReg, Disp, BaseReg, IndexReg, Scale, Start, End,  in CreateMemForMSInlineAsm()
2550   unsigned IndexReg = SM.getIndexReg();  in ParseIntelOperand()  local
2556       (IndexReg == X86::ESP || IndexReg == X86::RSP))  in ParseIntelOperand()
2557     std::swap(BaseReg, IndexReg);  in ParseIntelOperand()
2562       !(X86MCRegisterClasses[X86::VR128XRegClassID].contains(IndexReg) ||  in ParseIntelOperand()
2563         X86MCRegisterClasses[X86::VR256XRegClassID].contains(IndexReg) ||  in ParseIntelOperand()
2564         X86MCRegisterClasses[X86::VR512RegClassID].contains(IndexReg)) &&  in ParseIntelOperand()
2568     std::swap(BaseReg, IndexReg);  in ParseIntelOperand()
2571       X86MCRegisterClasses[X86::GR16RegClassID].contains(IndexReg))  in ParseIntelOperand()
2582       (IndexReg == X86::BX || IndexReg == X86::BP))  in ParseIntelOperand()
2583     std::swap(BaseReg, IndexReg);  in ParseIntelOperand()
2585   if ((BaseReg || IndexReg) &&  in ParseIntelOperand()
2586       CheckBaseRegAndIndexRegAndScale(BaseReg, IndexReg, Scale, is64BitMode(),  in ParseIntelOperand()
2590     return CreateMemForMSInlineAsm(RegNo, Disp, BaseReg, IndexReg, Scale, Start,  in ParseIntelOperand()
2598                                              BaseReg, IndexReg, Scale, Start,  in ParseIntelOperand()
2604   if ((BaseReg || IndexReg || RegNo))  in ParseIntelOperand()
2606                                              BaseReg, IndexReg, Scale, Start,  in ParseIntelOperand()
2903   unsigned BaseReg = 0, IndexReg = 0, Scale = 1;  in ParseMemOperand()  local
2942         IndexReg = cast<X86MCExpr>(E)->getRegNo();  in ParseMemOperand()
2947         if (IndexReg == X86::RIP)  in ParseMemOperand()
2980   if (BaseReg == X86::DX && IndexReg == 0 && Scale == 1 && SegReg == 0 &&  in ParseMemOperand()
2987   if (CheckBaseRegAndIndexRegAndScale(BaseReg, IndexReg, Scale, is64BitMode(),  in ParseMemOperand()
2991   if (SegReg || BaseReg || IndexReg)  in ParseMemOperand()
2993                                              BaseReg, IndexReg, Scale, StartLoc,  in ParseMemOperand()