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Lines Matching refs:OpReg

1739         Register OpReg = getRegForValue(TI->getOperand(0));  in X86SelectBranch()  local
1740 if (OpReg == 0) return false; in X86SelectBranch()
1743 .addReg(OpReg).addImm(1); in X86SelectBranch()
1774 Register OpReg = getRegForValue(BI->getCondition()); in X86SelectBranch() local
1775 if (OpReg == 0) return false; in X86SelectBranch()
1778 if (MRI.getRegClass(OpReg) == &X86::VK1RegClass) { in X86SelectBranch()
1779 unsigned KOpReg = OpReg; in X86SelectBranch()
1780 OpReg = createResultReg(&X86::GR32RegClass); in X86SelectBranch()
1782 TII.get(TargetOpcode::COPY), OpReg) in X86SelectBranch()
1784 OpReg = fastEmitInst_extractsubreg(MVT::i8, OpReg, /*Op0IsKill=*/true, in X86SelectBranch()
1788 .addReg(OpReg) in X86SelectBranch()
1797 unsigned CReg = 0, OpReg = 0; in X86SelectShift() local
1803 case Instruction::LShr: OpReg = X86::SHR8rCL; break; in X86SelectShift()
1804 case Instruction::AShr: OpReg = X86::SAR8rCL; break; in X86SelectShift()
1805 case Instruction::Shl: OpReg = X86::SHL8rCL; break; in X86SelectShift()
1813 case Instruction::LShr: OpReg = X86::SHR16rCL; break; in X86SelectShift()
1814 case Instruction::AShr: OpReg = X86::SAR16rCL; break; in X86SelectShift()
1815 case Instruction::Shl: OpReg = X86::SHL16rCL; break; in X86SelectShift()
1822 case Instruction::LShr: OpReg = X86::SHR32rCL; break; in X86SelectShift()
1823 case Instruction::AShr: OpReg = X86::SAR32rCL; break; in X86SelectShift()
1824 case Instruction::Shl: OpReg = X86::SHL32rCL; break; in X86SelectShift()
1831 case Instruction::LShr: OpReg = X86::SHR64rCL; break; in X86SelectShift()
1832 case Instruction::AShr: OpReg = X86::SAR64rCL; break; in X86SelectShift()
1833 case Instruction::Shl: OpReg = X86::SHL64rCL; break; in X86SelectShift()
1859 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(OpReg), ResultReg) in X86SelectShift()
2392 Register OpReg = getRegForValue(Opnd); in X86SelectSelect() local
2393 if (OpReg == 0) in X86SelectSelect()
2400 .addReg(OpReg, getKillRegState(OpIsKill)); in X86SelectSelect()
2438 Register OpReg = getRegForValue(I->getOperand(0)); in X86SelectIntToFP() local
2439 if (OpReg == 0) in X86SelectIntToFP()
2471 fastEmitInst_rr(Opcode, RC, ImplicitDefReg, true, OpReg, false); in X86SelectIntToFP()
2493 Register OpReg = getRegForValue(I->getOperand(0)); in X86SelectFPExtOrFPTrunc() local
2494 if (OpReg == 0) in X86SelectFPExtOrFPTrunc()
2513 MIB.addReg(OpReg); in X86SelectFPExtOrFPTrunc()