Lines Matching refs:ResultReg
88 unsigned &ResultReg, unsigned Alignment = 1);
97 unsigned &ResultReg);
318 MachineMemOperand *MMO, unsigned &ResultReg, in X86FastEmitLoad() argument
469 ResultReg = createResultReg(RC); in X86FastEmitLoad()
471 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc), ResultReg); in X86FastEmitLoad()
706 unsigned &ResultReg) { in X86FastEmitExtend() argument
712 ResultReg = RR; in X86FastEmitExtend()
1346 unsigned ResultReg = 0; in X86SelectLoad() local
1347 if (!X86FastEmitLoad(VT, AM, createMachineMemOperandFor(LI), ResultReg, in X86SelectLoad()
1351 updateValueMap(I, ResultReg); in X86SelectLoad()
1451 unsigned ResultReg = 0; in X86SelectCmp() local
1455 ResultReg = createResultReg(&X86::GR32RegClass); in X86SelectCmp()
1457 ResultReg); in X86SelectCmp()
1458 ResultReg = fastEmitInst_extractsubreg(MVT::i8, ResultReg, in X86SelectCmp()
1460 if (!ResultReg) in X86SelectCmp()
1465 ResultReg = createResultReg(&X86::GR8RegClass); in X86SelectCmp()
1467 ResultReg).addImm(1); in X86SelectCmp()
1472 if (ResultReg) { in X86SelectCmp()
1473 updateValueMap(I, ResultReg); in X86SelectCmp()
1501 ResultReg = createResultReg(&X86::GR8RegClass); in X86SelectCmp()
1513 ResultReg).addReg(FlagReg1).addReg(FlagReg2); in X86SelectCmp()
1514 updateValueMap(I, ResultReg); in X86SelectCmp()
1531 ResultReg).addImm(CC); in X86SelectCmp()
1532 updateValueMap(I, ResultReg); in X86SelectCmp()
1541 Register ResultReg = getRegForValue(I->getOperand(0)); in X86SelectZExt() local
1542 if (ResultReg == 0) in X86SelectZExt()
1549 ResultReg = fastEmitZExtFromI1(MVT::i8, ResultReg, /*TODO: Kill=*/false); in X86SelectZExt()
1552 if (ResultReg == 0) in X86SelectZExt()
1569 .addReg(ResultReg); in X86SelectZExt()
1571 ResultReg = createResultReg(&X86::GR64RegClass); in X86SelectZExt()
1573 ResultReg) in X86SelectZExt()
1580 Result32).addReg(ResultReg); in X86SelectZExt()
1582 ResultReg = fastEmitInst_extractsubreg(MVT::i16, Result32, in X86SelectZExt()
1585 ResultReg = fastEmit_r(MVT::i8, DstVT.getSimpleVT(), ISD::ZERO_EXTEND, in X86SelectZExt()
1586 ResultReg, /*Op0IsKill=*/true); in X86SelectZExt()
1587 if (ResultReg == 0) in X86SelectZExt()
1591 updateValueMap(I, ResultReg); in X86SelectZExt()
1600 Register ResultReg = getRegForValue(I->getOperand(0)); in X86SelectSExt() local
1601 if (ResultReg == 0) in X86SelectSExt()
1608 Register ZExtReg = fastEmitZExtFromI1(MVT::i8, ResultReg, in X86SelectSExt()
1614 ResultReg = createResultReg(&X86::GR8RegClass); in X86SelectSExt()
1616 ResultReg).addReg(ZExtReg); in X86SelectSExt()
1626 Result32).addReg(ResultReg); in X86SelectSExt()
1628 ResultReg = fastEmitInst_extractsubreg(MVT::i16, Result32, in X86SelectSExt()
1631 ResultReg = fastEmit_r(MVT::i8, DstVT.getSimpleVT(), ISD::SIGN_EXTEND, in X86SelectSExt()
1632 ResultReg, /*Op0IsKill=*/true); in X86SelectSExt()
1633 if (ResultReg == 0) in X86SelectSExt()
1637 updateValueMap(I, ResultReg); in X86SelectSExt()
1858 Register ResultReg = createResultReg(RC); in X86SelectShift() local
1859 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(OpReg), ResultReg) in X86SelectShift()
1861 updateValueMap(I, ResultReg); in X86SelectShift()
2001 unsigned ResultReg = 0; in X86SelectDivRem() local
2015 ResultReg = fastEmitInst_extractsubreg(MVT::i8, ResultSuperReg, in X86SelectDivRem()
2019 if (!ResultReg) { in X86SelectDivRem()
2020 ResultReg = createResultReg(TypeEntry.RC); in X86SelectDivRem()
2021 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Copy), ResultReg) in X86SelectDivRem()
2024 updateValueMap(I, ResultReg); in X86SelectDivRem()
2152 Register ResultReg = fastEmitInst_rri(Opc, RC, RHSReg, RHSIsKill, in X86FastEmitCMoveSelect() local
2154 updateValueMap(I, ResultReg); in X86FastEmitCMoveSelect()
2217 unsigned ResultReg; in X86FastEmitSSESelect() local
2243 ResultReg = createResultReg(RC); in X86FastEmitSSESelect()
2245 TII.get(TargetOpcode::COPY), ResultReg).addReg(MovReg); in X86FastEmitSSESelect()
2264 ResultReg = createResultReg(RC); in X86FastEmitSSESelect()
2266 TII.get(TargetOpcode::COPY), ResultReg).addReg(VBlendReg); in X86FastEmitSSESelect()
2290 ResultReg = createResultReg(RC); in X86FastEmitSSESelect()
2292 TII.get(TargetOpcode::COPY), ResultReg).addReg(OrReg); in X86FastEmitSSESelect()
2294 updateValueMap(I, ResultReg); in X86FastEmitSSESelect()
2370 Register ResultReg = in X86FastEmitPseudoSelect() local
2372 updateValueMap(I, ResultReg); in X86FastEmitPseudoSelect()
2397 Register ResultReg = createResultReg(RC); in X86SelectSelect() local
2399 TII.get(TargetOpcode::COPY), ResultReg) in X86SelectSelect()
2401 updateValueMap(I, ResultReg); in X86SelectSelect()
2470 Register ResultReg = in X86SelectIntToFP() local
2472 updateValueMap(I, ResultReg); in X86SelectIntToFP()
2505 Register ResultReg = createResultReg(RC); in X86SelectFPExtOrFPTrunc() local
2508 ResultReg); in X86SelectFPExtOrFPTrunc()
2514 updateValueMap(I, ResultReg); in X86SelectFPExtOrFPTrunc()
2568 Register ResultReg = fastEmitInst_extractsubreg(MVT::i8, in X86SelectTrunc() local
2571 if (!ResultReg) in X86SelectTrunc()
2574 updateValueMap(I, ResultReg); in X86SelectTrunc()
2641 unsigned ResultReg = 0; in fastLowerIntrinsicCall() local
2658 ResultReg = createResultReg(&X86::GR32RegClass); in fastLowerIntrinsicCall()
2659 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc), ResultReg) in fastLowerIntrinsicCall()
2664 ResultReg = fastEmitInst_extractsubreg(MVT::i16, ResultReg, true, RegIdx); in fastLowerIntrinsicCall()
2681 ResultReg = createResultReg(TLI.getRegClassFor(MVT::f32)); in fastLowerIntrinsicCall()
2683 TII.get(TargetOpcode::COPY), ResultReg) in fastLowerIntrinsicCall()
2687 updateValueMap(II, ResultReg); in fastLowerIntrinsicCall()
2866 Register ResultReg = createResultReg(RC); in fastLowerIntrinsicCall() local
2869 ResultReg); in fastLowerIntrinsicCall()
2876 updateValueMap(II, ResultReg); in fastLowerIntrinsicCall()
2930 unsigned ResultReg = 0; in fastLowerIntrinsicCall() local
2941 ResultReg = createResultReg(TLI.getRegClassFor(VT)); in fastLowerIntrinsicCall()
2944 TII.get(Opc[IsDec][VT.SimpleTy-MVT::i8]), ResultReg) in fastLowerIntrinsicCall()
2947 ResultReg = fastEmit_ri(VT, VT, BaseOpc, LHSReg, LHSIsKill, in fastLowerIntrinsicCall()
2953 if (!ResultReg) { in fastLowerIntrinsicCall()
2958 ResultReg = fastEmit_rr(VT, VT, BaseOpc, LHSReg, LHSIsKill, RHSReg, in fastLowerIntrinsicCall()
2964 if (BaseOpc == X86ISD::UMUL && !ResultReg) { in fastLowerIntrinsicCall()
2973 ResultReg = fastEmitInst_r(MULOpc[VT.SimpleTy-MVT::i8], in fastLowerIntrinsicCall()
2975 } else if (BaseOpc == X86ISD::SMUL && !ResultReg) { in fastLowerIntrinsicCall()
2984 ResultReg = fastEmitInst_r(MULOpc[0], TLI.getRegClassFor(VT), RHSReg, in fastLowerIntrinsicCall()
2987 ResultReg = fastEmitInst_rr(MULOpc[VT.SimpleTy-MVT::i8], in fastLowerIntrinsicCall()
2992 if (!ResultReg) in fastLowerIntrinsicCall()
2997 assert((ResultReg+1) == ResultReg2 && "Nonconsecutive result registers."); in fastLowerIntrinsicCall()
3001 updateValueMap(II, ResultReg, 2); in fastLowerIntrinsicCall()
3067 Register ResultReg = createResultReg(TLI.getRegClassFor(VT)); in fastLowerIntrinsicCall() local
3068 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc), ResultReg) in fastLowerIntrinsicCall()
3071 updateValueMap(II, ResultReg); in fastLowerIntrinsicCall()
3165 Register ResultReg = createResultReg(RC); in fastLowerArguments() local
3167 TII.get(TargetOpcode::COPY), ResultReg) in fastLowerArguments()
3169 updateValueMap(&Arg, ResultReg); in fastLowerArguments()
3288 unsigned ResultReg; in fastLowerCall() local
3292 ResultReg = getRegForValue(PrevVal); in fastLowerCall()
3294 if (!ResultReg) in fastLowerCall()
3300 ResultReg = in fastLowerCall()
3301 fastEmit_ri(VT, VT, ISD::AND, ResultReg, hasTrivialKill(PrevVal), 1); in fastLowerCall()
3306 ResultReg = getRegForValue(Val); in fastLowerCall()
3309 if (!ResultReg) in fastLowerCall()
3312 ArgRegs.push_back(ResultReg); in fastLowerCall()
3569 Register ResultReg = FuncInfo.CreateRegs(CLI.RetTy); in fastLowerCall() local
3573 unsigned CopyReg = ResultReg + i; in fastLowerCall()
3608 TII.get(Opc), ResultReg + i), FI); in fastLowerCall()
3612 CLI.ResultReg = ResultReg; in fastLowerCall()
3695 Register ResultReg = createResultReg(DstClass); in fastSelectInstruction() local
3697 TII.get(TargetOpcode::COPY), ResultReg).addReg(Reg); in fastSelectInstruction()
3699 updateValueMap(I, ResultReg); in fastSelectInstruction()
3726 Register ResultReg = createResultReg(&X86::GR64RegClass); in X86MaterializeInt() local
3728 TII.get(TargetOpcode::SUBREG_TO_REG), ResultReg) in X86MaterializeInt()
3730 return ResultReg; in X86MaterializeInt()
3808 Register ResultReg = createResultReg(TLI.getRegClassFor(VT.SimpleTy)); in X86MaterializeFP() local
3817 TII.get(Opc), ResultReg); in X86MaterializeFP()
3823 return ResultReg; in X86MaterializeFP()
3827 TII.get(Opc), ResultReg), in X86MaterializeFP()
3829 return ResultReg; in X86MaterializeFP()
3846 Register ResultReg = createResultReg(TLI.getRegClassFor(VT)); in X86MaterializeGV() local
3852 ResultReg) in X86MaterializeGV()
3860 TII.get(Opc), ResultReg), AM); in X86MaterializeGV()
3862 return ResultReg; in X86MaterializeGV()
3905 Register ResultReg = createResultReg(RC); in fastMaterializeAlloca() local
3907 TII.get(Opc), ResultReg), AM); in fastMaterializeAlloca()
3908 return ResultReg; in fastMaterializeAlloca()
3938 Register ResultReg = createResultReg(TLI.getRegClassFor(VT)); in fastMaterializeFloatZero() local
3939 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc), ResultReg); in fastMaterializeFloatZero()
3940 return ResultReg; in fastMaterializeFloatZero()
3998 Register ResultReg = createResultReg(RC); in fastEmitInst_rrrr() local
4005 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, II, ResultReg) in fastEmitInst_rrrr()
4017 TII.get(TargetOpcode::COPY), ResultReg).addReg(II.ImplicitDefs[0]); in fastEmitInst_rrrr()
4019 return ResultReg; in fastEmitInst_rrrr()