Lines Matching refs:IndexReg
385 Register IndexReg = Index.getReg(); in optTwoAddrLEA() local
395 if (IndexReg != 0) in optTwoAddrLEA()
396 IndexReg = TRI->getSubReg(IndexReg, X86::sub_32bit); in optTwoAddrLEA()
403 if (BaseReg != 0 && IndexReg != 0 && Disp.getImm() == 0 && in optTwoAddrLEA()
404 (DestReg == BaseReg || DestReg == IndexReg)) { in optTwoAddrLEA()
407 std::swap(BaseReg, IndexReg); in optTwoAddrLEA()
412 .addReg(BaseReg).addReg(IndexReg) in optTwoAddrLEA()
417 .addReg(BaseReg).addReg(IndexReg); in optTwoAddrLEA()
419 } else if (DestReg == BaseReg && IndexReg == 0) { in optTwoAddrLEA()
570 Register IndexReg = Index.getReg(); in processInstrForSlow3OpLEA() local
575 if (IndexReg != 0) in processInstrForSlow3OpLEA()
576 IndexReg = TRI->getSubReg(IndexReg, X86::sub_32bit); in processInstrForSlow3OpLEA()
581 bool IsInefficientIndex = isInefficientLEAReg(IndexReg); in processInstrForSlow3OpLEA()
597 if (IsScale1 && (DestReg == BaseReg || DestReg == IndexReg)) { in processInstrForSlow3OpLEA()
600 std::swap(BaseReg, IndexReg); in processInstrForSlow3OpLEA()
606 .addReg(IndexReg) in processInstrForSlow3OpLEA()
612 .addReg(IndexReg); in processInstrForSlow3OpLEA()
666 bool BIK = Base.isKill() && BaseReg != IndexReg; in processInstrForSlow3OpLEA()