Lines Matching refs:INSERT_SUBVECTOR
790 setOperationAction(ISD::INSERT_SUBVECTOR, VT,Expand); in X86TargetLowering()
1378 setOperationAction(ISD::INSERT_SUBVECTOR, VT, Legal); in X86TargetLowering()
1464 setOperationAction(ISD::INSERT_SUBVECTOR, VT, Custom); in X86TargetLowering()
1686 setOperationAction(ISD::INSERT_SUBVECTOR, VT, Legal); in X86TargetLowering()
1846 setOperationAction(ISD::INSERT_SUBVECTOR, VT, Custom); in X86TargetLowering()
1975 setTargetDAGCombine(ISD::INSERT_SUBVECTOR); in X86TargetLowering()
5876 return DAG.getNode(ISD::INSERT_SUBVECTOR, dl, ResultVT, Result, Vec, VecIdx); in insertSubVector()
5901 return DAG.getNode(ISD::INSERT_SUBVECTOR, dl, VT, Res, Vec, in widenSubVector()
5930 if (N->getOpcode() == ISD::INSERT_SUBVECTOR) { in collectConcatOps()
5941 if (Src.getOpcode() == ISD::INSERT_SUBVECTOR && in collectConcatOps()
6104 Op = DAG.getNode(ISD::INSERT_SUBVECTOR, dl, WideOpVT, in insert1BitVector()
6121 Vec = DAG.getNode(ISD::INSERT_SUBVECTOR, dl, WideOpVT, Undef, Vec, in insert1BitVector()
6126 SubVec = DAG.getNode(ISD::INSERT_SUBVECTOR, dl, WideOpVT, in insert1BitVector()
6133 SubVec = DAG.getNode(ISD::INSERT_SUBVECTOR, dl, WideOpVT, in insert1BitVector()
6164 Vec = DAG.getNode(ISD::INSERT_SUBVECTOR, dl, WideOpVT, in insert1BitVector()
6169 Vec = DAG.getNode(ISD::INSERT_SUBVECTOR, dl, WideOpVT, in insert1BitVector()
6185 Vec = DAG.getNode(ISD::INSERT_SUBVECTOR, dl, WideOpVT, Undef, Vec, ZeroIdx); in insert1BitVector()
6658 if (Op.getOpcode() == ISD::INSERT_SUBVECTOR) { in getTargetConstantBitsFromNode()
7342 if (V.getOpcode() == ISD::INSERT_SUBVECTOR) { in getTargetShuffleAndZeroables()
7501 case ISD::INSERT_SUBVECTOR: { in getFauxShuffleMask()
7910 if (Opcode == ISD::INSERT_SUBVECTOR) { in getShuffleScalarElt()
8530 return DAG.getNode(ISD::INSERT_SUBVECTOR, DL, VT, DAG.getUNDEF(VT), in EltsFromConsecutiveLoads()
10551 Vec = DAG.getNode(ISD::INSERT_SUBVECTOR, dl, ResVT, Vec, in LowerAVXCONCAT_VECTORS()
10599 SubVec = DAG.getNode(ISD::INSERT_SUBVECTOR, dl, ShiftVT, in LowerCONCAT_VECTORSvXi1()
10616 return DAG.getNode(ISD::INSERT_SUBVECTOR, dl, ResVT, Vec, SubVec, in LowerCONCAT_VECTORSvXi1()
10635 SDValue Vec = DAG.getNode(ISD::INSERT_SUBVECTOR, dl, ResVT, in LowerCONCAT_VECTORSvXi1()
10638 return DAG.getNode(ISD::INSERT_SUBVECTOR, dl, ResVT, Vec, Op.getOperand(1), in LowerCONCAT_VECTORSvXi1()
13489 case ISD::INSERT_SUBVECTOR: { in lowerShuffleAsBroadcast()
15865 return DAG.getNode(ISD::INSERT_SUBVECTOR, DL, VT, in lowerV2X128Shuffle()
15894 return DAG.getNode(ISD::INSERT_SUBVECTOR, DL, VT, V1, SubVec, in lowerV2X128Shuffle()
16200 return DAG.getNode(ISD::INSERT_SUBVECTOR, DL, VT, DAG.getUNDEF(VT), V, in getShuffleHalfVectors()
16229 return DAG.getNode(ISD::INSERT_SUBVECTOR, DL, VT, DAG.getUNDEF(VT), Hi, in lowerShuffleWithUndefHalf()
16239 return DAG.getNode(ISD::INSERT_SUBVECTOR, DL, VT, DAG.getUNDEF(VT), Hi, in lowerShuffleWithUndefHalf()
16598 return DAG.getNode(ISD::INSERT_SUBVECTOR, DL, MVT::v32i8, in lowerShuffleAsVTRUNCAndUnpack()
17358 return DAG.getNode(ISD::INSERT_SUBVECTOR, DL, VT, in lowerV4X128Shuffle()
17372 return DAG.getNode(ISD::INSERT_SUBVECTOR, DL, VT, V1, SubVec, in lowerV4X128Shuffle()
17937 SDValue Res = DAG.getNode(ISD::INSERT_SUBVECTOR, DL, WideVT, in lower1BitShuffleAsKSHIFTR()
18021 return DAG.getNode(ISD::INSERT_SUBVECTOR, DL, VT, in lower1BitShuffle()
18040 SDValue Res = DAG.getNode(ISD::INSERT_SUBVECTOR, DL, WideVT, in lower1BitShuffle()
18503 Vec = DAG.getNode(ISD::INSERT_SUBVECTOR, dl, WideVecVT, in ExtractBitFromMaskVector()
18685 return DAG.getNode(ISD::INSERT_SUBVECTOR, dl, VecVT, Vec, EltInVec, Idx); in InsertBitToMaskVector()
18897 Vec = DAG.getNode(ISD::INSERT_SUBVECTOR, dl, WideVecVT, in LowerEXTRACT_SUBVECTOR()
19702 Src = DAG.getNode(ISD::INSERT_SUBVECTOR, DL, MVT::v8i64, Tmp, Src, in lowerINT_TO_FP_vXi64()
20105 V = DAG.getNode(ISD::INSERT_SUBVECTOR, DL, WideIntVT, Tmp, V, in lowerUINT_TO_FP_vXi32()
20656 In = DAG.getNode(ISD::INSERT_SUBVECTOR, DL, InVT, DAG.getUNDEF(InVT), in LowerZERO_EXTEND_Mask()
21068 Src = DAG.getNode(ISD::INSERT_SUBVECTOR, dl, MVT::v8f64, Tmp, Src, in LowerFP_TO_INT()
21108 Src = DAG.getNode(ISD::INSERT_SUBVECTOR, dl, WideVT, Tmp, Src, in LowerFP_TO_INT()
21139 Src = DAG.getNode(ISD::INSERT_SUBVECTOR, dl, WideVT, Tmp, Src, in LowerFP_TO_INT()
23622 In = DAG.getNode(ISD::INSERT_SUBVECTOR, dl, InVT, DAG.getUNDEF(InVT), in LowerSIGN_EXTEND_Mask()
23917 StoredVal = DAG.getNode(ISD::INSERT_SUBVECTOR, dl, MVT::v16i1, in LowerStore()
25089 SDValue Ins = DAG.getNode(ISD::INSERT_SUBVECTOR, dl, MVT::v8i1, in LowerINTRINSIC_WO_CHAIN()
25136 SDValue Ins = DAG.getNode(ISD::INSERT_SUBVECTOR, dl, MVT::v8i1, in LowerINTRINSIC_WO_CHAIN()
25195 SDValue Ins = DAG.getNode(ISD::INSERT_SUBVECTOR, dl, MVT::v16i1, in LowerINTRINSIC_WO_CHAIN()
29407 return DAG.getNode(ISD::INSERT_SUBVECTOR, dl, NVT, FillVal, in ExtendToType()
29730 case ISD::INSERT_SUBVECTOR: return LowerINSERT_SUBVECTOR(Op, Subtarget,DAG); in LowerOperation()
35112 if (Src.getOpcode() == ISD::INSERT_SUBVECTOR && in combineX86ShuffleChain()
35132 if (Depth == 0 && Root.getOpcode() == ISD::INSERT_SUBVECTOR) in combineX86ShuffleChain()
35205 if (Depth == 0 && Root.getOpcode() == ISD::INSERT_SUBVECTOR) in combineX86ShuffleChain()
36930 if (V.getOpcode() == ISD::INSERT_SUBVECTOR && V.getOperand(0).isUndef() && in combineTargetShuffle()
36938 return DAG.getNode(ISD::INSERT_SUBVECTOR, DL, VT, in combineTargetShuffle()
36994 Ins0.getOpcode() == ISD::INSERT_SUBVECTOR && in combineTargetShuffle()
36995 Ins1.getOpcode() == ISD::INSERT_SUBVECTOR && in combineTargetShuffle()
39074 return DAG.getNode(ISD::INSERT_SUBVECTOR, DL, VT, in combineBitcastToBoolVector()
40898 Cond = DAG.getNode(ISD::INSERT_SUBVECTOR, DL, SrcCondVT, in combineSelect()
43079 SDValue Ins = DAG.getNode(ISD::INSERT_SUBVECTOR, DL, MVT::v16i1, in combineCompareEqual()
47226 return DAG.getNode(ISD::INSERT_SUBVECTOR, DL, VecVT, in combineVectorSizedSetCCEquality()
48993 if (SubVec.getOpcode() == ISD::INSERT_SUBVECTOR && in combineInsertSubvector()
48996 return DAG.getNode(ISD::INSERT_SUBVECTOR, dl, OpVT, in combineInsertSubvector()
49008 SubVec.getOperand(0).getOpcode() == ISD::INSERT_SUBVECTOR) { in combineInsertSubvector()
49014 return DAG.getNode(ISD::INSERT_SUBVECTOR, dl, OpVT, in combineInsertSubvector()
49060 return DAG.getNode(ISD::INSERT_SUBVECTOR, dl, OpVT, in combineInsertSubvector()
49213 InVec.getOpcode() == ISD::INSERT_SUBVECTOR && IdxVal == 0 && in combineExtractSubvector()
49218 return DAG.getNode(ISD::INSERT_SUBVECTOR, DL, VT, in combineExtractSubvector()
49734 case ISD::INSERT_SUBVECTOR: in PerformDAGCombine()