Lines Matching refs:STRICT_FSUB
626 setOperationAction(ISD::STRICT_FSUB, MVT::f32, Legal); in X86TargetLowering()
627 setOperationAction(ISD::STRICT_FSUB, MVT::f64, Legal); in X86TargetLowering()
680 setOperationAction(ISD::STRICT_FSUB , MVT::f80, Legal); in X86TargetLowering()
700 setOperationAction(ISD::STRICT_FSUB, MVT::f128, LibCall); in X86TargetLowering()
864 setOperationAction(ISD::STRICT_FSUB, MVT::v4f32, Legal); in X86TargetLowering()
1056 setOperationAction(ISD::STRICT_FSUB, MVT::v2f64, Legal); in X86TargetLowering()
1217 setOperationAction(ISD::STRICT_FSUB, MVT::v8f32, Legal); in X86TargetLowering()
1218 setOperationAction(ISD::STRICT_FSUB, MVT::v4f64, Legal); in X86TargetLowering()
1521 setOperationAction(ISD::STRICT_FSUB, MVT::v16f32, Legal); in X86TargetLowering()
1522 setOperationAction(ISD::STRICT_FSUB, MVT::v8f64, Legal); in X86TargetLowering()
20005 SDValue Sub = DAG.getNode(ISD::STRICT_FSUB, dl, {MVT::f64, MVT::Other}, in LowerUINT_TO_FP_i32()
20074 return DAG.getNode(ISD::STRICT_FSUB, DL, {MVT::v2f64, MVT::Other}, in lowerUINT_TO_FP_v2i32()
20144 return DAG.getNode(ISD::STRICT_FSUB, DL, {MVT::v4f64, MVT::Other}, in lowerUINT_TO_FP_vXi32()
20226 SDValue FHigh = DAG.getNode(ISD::STRICT_FSUB, DL, {VecFloatVT, MVT::Other}, in lowerUINT_TO_FP_vXi32()
20504 Value = DAG.getNode(ISD::STRICT_FSUB, DL, { TheVT, MVT::Other}, in FP_TO_INTHelper()
30409 SDValue Sub = DAG.getNode(ISD::STRICT_FSUB, dl, {MVT::v2f64, MVT::Other}, in ReplaceNodeResults()