7701   case X86ISD::VSRLI: {  in getFauxShuffleMask()
12358     SDValue SRL = DAG.getNode(X86ISD::VSRLI, DL, RotateVT, V1,  in lowerShuffleAsBitRotate()
12673                   : (ByteShift ? X86ISD::VSRLDQ : X86ISD::VSRLI);  in matchShuffleAsShift()
24395   case X86ISD::VSRLI:  in getTargetVShiftUniformOpcode()
24396     return IsVariable ? X86ISD::VSRL : X86ISD::VSRLI;  in getTargetVShiftUniformOpcode()
24429   assert((Opc == X86ISD::VSHLI || Opc == X86ISD::VSRLI || Opc == X86ISD::VSRAI)  in getTargetVShiftByConstNode()
24453     case X86ISD::VSRLI:  in getTargetVShiftByConstNode()
27120     SDValue Bhi = getTargetVShiftByConstNode(X86ISD::VSRLI, dl, VT, B, 32, DAG);  in LowerMUL()
27126     SDValue Ahi = getTargetVShiftByConstNode(X86ISD::VSRLI, dl, VT, A, 32, DAG);  in LowerMUL()
27235     Mul = getTargetVShiftByConstNode(X86ISD::VSRLI, dl, ExVT, Mul, 8, DAG);  in LowerMULH()
27320   RLo = getTargetVShiftByConstNode(X86ISD::VSRLI, dl, ExVT, RLo, 8, DAG);  in LowerMULH()
27321   RHi = getTargetVShiftByConstNode(X86ISD::VSRLI, dl, ExVT, RHi, 8, DAG);  in LowerMULH()
27467           getTargetVShiftByConstNode(X86ISD::VSRLI, dl, VT, R, ShiftAmt, DAG);  in LowerScalarImmediateShift()
27533       SDValue SRL = getTargetVShiftByConstNode(X86ISD::VSRLI, dl, ShiftVT, R,  in LowerScalarImmediateShift()
27965       R = DAG.getNode(X86ISD::VSRLI, dl, ExVT, R, Cst8);  in LowerShift()
27987     LoR = DAG.getNode(X86ISD::VSRLI, dl, VT16, LoR, Cst8);  in LowerShift()
27988     HiR = DAG.getNode(X86ISD::VSRLI, dl, VT16, HiR, Cst8);  in LowerShift()
28095       RLo = getTargetVShiftByConstNode(X86ISD::VSRLI, dl, ExtVT, RLo, 8, DAG);  in LowerShift()
28096       RHi = getTargetVShiftByConstNode(X86ISD::VSRLI, dl, ExtVT, RHi, 8, DAG);  in LowerShift()
28114     Lo = getTargetVShiftByConstNode(X86ISD::VSRLI, dl, ExtVT, Lo, 16, DAG);  in LowerShift()
28115     Hi = getTargetVShiftByConstNode(X86ISD::VSRLI, dl, ExtVT, Hi, 16, DAG);  in LowerShift()
30863   NODE_NAME_CASE(VSRLI)  in getTargetNodeName()
34087   case X86ISD::VSRLI: {  in computeKnownBitsForTargetNode()
34100     } else if (Opc == X86ISD::VSRLI) {  in computeKnownBitsForTargetNode()
37751   case X86ISD::VSRLI:  in SimplifyDemandedVectorEltsForTargetNode()
38030     case X86ISD::VSRLI:  in SimplifyDemandedVectorEltsForTargetNode()
38250     if (Op0.getOpcode() == X86ISD::VSRLI &&  in SimplifyDemandedBitsForTargetNode()
38258         unsigned NewOpc = Diff < 0 ? X86ISD::VSRLI : X86ISD::VSHLI;  in SimplifyDemandedBitsForTargetNode()
38286   case X86ISD::VSRLI: {  in SimplifyDemandedBitsForTargetNode()
38347           Op, TLO.DAG.getNode(X86ISD::VSRLI, SDLoc(Op), VT, Op0, Op1));  in SimplifyDemandedBitsForTargetNode()
42895           X86ISD::VSRLI == Opcode) &&  in combineVectorShiftImm()
42897   bool LogicalShift = X86ISD::VSHLI == Opcode || X86ISD::VSRLI == Opcode;  in combineVectorShiftImm()
43362   SDValue Shift = DAG.getNode(X86ISD::VSRLI, DL, VT0, Op0, ShAmt);  in combineAndMaskToShift()
48850     case X86ISD::VSRLI:  in combineConcatVectorOps()
49820   case X86ISD::VSRLI:  in PerformDAGCombine()