Lines Matching refs:cntl
2683 def ri : Ii32<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, immtype:$cntl),
2685 "\t{$cntl, $src1, $dst|$dst, $src1, $cntl}"),
2686 [(set RC:$dst, (OpNode RC:$src1, immoperator:$cntl))]>,
2689 (ins x86memop:$src1, immtype:$cntl),
2691 "\t{$cntl, $src1, $dst|$dst, $src1, $cntl}"),
2692 [(set RC:$dst, (OpNode (ld_frag addr:$src1), immoperator:$cntl))]>,
2762 def rri : Ii32<0x12, MRM0r, (outs), (ins RC:$src0, GR32:$src1, i32imm:$cntl),
2763 "lwpins\t{$cntl, $src1, $src0|$src0, $src1, $cntl}",
2764 [(set EFLAGS, (X86lwpins RC:$src0, GR32:$src1, timm:$cntl))]>,
2767 def rmi : Ii32<0x12, MRM0m, (outs), (ins RC:$src0, i32mem:$src1, i32imm:$cntl),
2768 "lwpins\t{$cntl, $src1, $src0|$src0, $src1, $cntl}",
2769 [(set EFLAGS, (X86lwpins RC:$src0, (loadi32 addr:$src1), timm:$cntl))]>,
2779 def rri : Ii32<0x12, MRM1r, (outs), (ins RC:$src0, GR32:$src1, i32imm:$cntl),
2780 "lwpval\t{$cntl, $src1, $src0|$src0, $src1, $cntl}",
2781 [(Int RC:$src0, GR32:$src1, timm:$cntl)]>, XOP_4V, XOPA;
2783 def rmi : Ii32<0x12, MRM1m, (outs), (ins RC:$src0, i32mem:$src1, i32imm:$cntl),
2784 "lwpval\t{$cntl, $src1, $src0|$src0, $src1, $cntl}",
2785 [(Int RC:$src0, (loadi32 addr:$src1), timm:$cntl)]>,