Lines Matching refs:MRMSrcReg
26 def rr : SI<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2),
49 def rr_Int : SI_Int<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2),
72 def rr : PI<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2),
95 def rr : PI<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2),
194 def rr : SI<0x10, MRMSrcReg, (outs VR128:$dst),
340 def rr : PI<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src),
778 def VMOVLHPSrr : VPSI<0x16, MRMSrcReg, (outs VR128:$dst),
785 def VMOVHLPSrr : VPSI<0x12, MRMSrcReg, (outs VR128:$dst),
794 def MOVLHPSrr : PSI<0x16, MRMSrcReg, (outs VR128:$dst),
801 def MOVHLPSrr : PSI<0x12, MRMSrcReg, (outs VR128:$dst),
819 def rr : SI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src),
834 def rr : I<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src), asm,
849 def rr : SI<opc, MRMSrcReg, (outs DstRC:$dst), (ins DstRC:$src1, SrcRC:$src),
1000 def rr_Int : SI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src),
1016 def rr_Int : SI<opc, MRMSrcReg, (outs DstRC:$dst), (ins DstRC:$src1, SrcRC:$src2),
1246 def VCVTSD2SSrr : VSDI<0x5A, MRMSrcReg, (outs FR32:$dst),
1264 def CVTSD2SSrr : SDI<0x5A, MRMSrcReg, (outs FR32:$dst), (ins FR64:$src),
1276 def VCVTSD2SSrr_Int: I<0x5A, MRMSrcReg,
1291 def CVTSD2SSrr_Int: I<0x5A, MRMSrcReg,
1310 def VCVTSS2SDrr : I<0x5A, MRMSrcReg, (outs FR64:$dst),
1330 def CVTSS2SDrr : I<0x5A, MRMSrcReg, (outs FR64:$dst), (ins FR32:$src),
1342 def VCVTSS2SDrr_Int: I<0x5A, MRMSrcReg,
1354 def CVTSS2SDrr_Int: I<0x5A, MRMSrcReg,
1483 def VCVTPS2DQrr : VPDI<0x5B, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1492 def VCVTPS2DQYrr : VPDI<0x5B, MRMSrcReg, (outs VR256:$dst), (ins VR256:$src),
1503 def CVTPS2DQrr : PDI<0x5B, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1519 def VCVTPD2DQrr : SDI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1533 def VCVTPD2DQYrr : SDI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR256:$src),
1555 def CVTPD2DQrr : SDI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1565 def VCVTTPS2DQrr : VS2SI<0x5B, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1575 def VCVTTPS2DQYrr : VS2SI<0x5B, MRMSrcReg, (outs VR256:$dst), (ins VR256:$src),
1588 def CVTTPS2DQrr : S2SI<0x5B, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1605 def VCVTTPD2DQrr : VPDI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1617 def VCVTTPD2DQYrr : VPDI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR256:$src),
1641 def CVTTPD2DQrr : PDI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1655 def VCVTPS2PDrr : I<0x5A, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1663 def VCVTPS2PDYrr : I<0x5A, MRMSrcReg, (outs VR256:$dst), (ins VR128:$src),
1674 def CVTPS2PDrr : I<0x5A, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1695 def VCVTDQ2PDrr : S2SI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1706 def VCVTDQ2PDYrr : S2SI<0xE6, MRMSrcReg, (outs VR256:$dst), (ins VR128:$src),
1722 def CVTDQ2PDrr : S2SI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1746 def VCVTPD2PSrr : VPDI<0x5A, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1755 def VCVTPD2PSYrr : VPDI<0x5A, MRMSrcReg, (outs VR128:$dst), (ins VR256:$src),
1770 def CVTPD2PSrr : PDI<0x5A, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1789 def rr_Int : SIi8<0xC2, MRMSrcReg, (outs VR128:$dst),
1803 def rr : SIi8<0xC2, MRMSrcReg,
1843 def rr: SI<opc, MRMSrcReg, (outs), (ins RC:$src1, RC:$src2),
1863 def rr_Int: SI<opc, MRMSrcReg, (outs), (ins RC:$src1, RC:$src2),
1925 def rri : PIi8<0xC2, MRMSrcReg,
2024 def rri : PIi8<0xC6, MRMSrcReg, (outs RC:$dst),
2069 def rr : PI<opc, MRMSrcReg,
2159 def rr : PI<0x50, MRMSrcReg, (outs GR32orGR64:$dst), (ins RC:$src),
2211 def rr : PDI<opc, MRMSrcReg, (outs RC:$dst),
2795 def r : I<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src1),
2808 def r_Int : I<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
2861 def r : I<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2),
2870 def r_Int : I<opc, MRMSrcReg, (outs VR128:$dst),
2905 def V#NAME#PSr : PSI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
2915 def V#NAME#PSYr : PSI<opc, MRMSrcReg, (outs VR256:$dst), (ins VR256:$src),
2927 def PSr : PSI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
2941 def V#NAME#PDr : PDI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
2951 def V#NAME#PDYr : PDI<opc, MRMSrcReg, (outs VR256:$dst), (ins VR256:$src),
2963 def PDr : PDI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
3234 def VMOVDQArr : VPDI<0x6F, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
3237 def VMOVDQUrr : VSSI<0x6F, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
3240 def VMOVDQAYrr : VPDI<0x6F, MRMSrcReg, (outs VR256:$dst), (ins VR256:$src),
3243 def VMOVDQUYrr : VSSI<0x6F, MRMSrcReg, (outs VR256:$dst), (ins VR256:$src),
3310 def MOVDQArr : PDI<0x6F, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
3313 def MOVDQUrr : I<0x6F, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
3411 def rr : PDI<opc, MRMSrcReg, (outs RC:$dst),
3519 def rr : PDI<opc, MRMSrcReg, (outs RC:$dst),
3649 def V#NAME#ri : Ii8<0x70, MRMSrcReg, (outs VR128:$dst),
3667 def V#NAME#Yri : Ii8<0x70, MRMSrcReg, (outs VR256:$dst),
3685 def ri : Ii8<0x70, MRMSrcReg,
3720 def rr : PDI<opc, MRMSrcReg,
3745 def rr : SS48I<opc, MRMSrcReg,
3821 def rr : PDI<opc, MRMSrcReg,
3924 def rr : Ii8<0xC4, MRMSrcReg,
3947 def VPEXTRWrr : Ii8<0xC5, MRMSrcReg,
3953 def PEXTRWrr : PDIi8<0xC5, MRMSrcReg,
3975 def VPMOVMSKBrr : VPDI<0xD7, MRMSrcReg, (outs GR32orGR64:$dst),
3982 def VPMOVMSKBYrr : VPDI<0xD7, MRMSrcReg, (outs GR32orGR64:$dst),
3989 def PMOVMSKBrr : PDI<0xD7, MRMSrcReg, (outs GR32orGR64:$dst), (ins VR128:$src),
4002 def VMASKMOVDQU : VPDI<0xF7, MRMSrcReg, (outs),
4008 def VMASKMOVDQU64 : VPDI<0xF7, MRMSrcReg, (outs),
4015 def MASKMOVDQU : PDI<0xF7, MRMSrcReg, (outs), (ins VR128:$src, VR128:$mask),
4019 def MASKMOVDQU64 : PDI<0xF7, MRMSrcReg, (outs), (ins VR128:$src, VR128:$mask),
4033 def VMOVDI2PDIrr : VS2I<0x6E, MRMSrcReg, (outs VR128:$dst), (ins GR32:$src),
4043 def VMOV64toPQIrr : VRS2I<0x6E, MRMSrcReg, (outs VR128:$dst), (ins GR64:$src),
4053 def VMOV64toSDrr : VRS2I<0x6E, MRMSrcReg, (outs FR64:$dst), (ins GR64:$src),
4058 def MOVDI2PDIrr : S2I<0x6E, MRMSrcReg, (outs VR128:$dst), (ins GR32:$src),
4068 def MOV64toPQIrr : RS2I<0x6E, MRMSrcReg, (outs VR128:$dst), (ins GR64:$src),
4078 def MOV64toSDrr : RS2I<0x6E, MRMSrcReg, (outs FR64:$dst), (ins GR64:$src),
4088 def VMOVDI2SSrr : VS2I<0x6E, MRMSrcReg, (outs FR32:$dst), (ins GR32:$src),
4093 def MOVDI2SSrr : S2I<0x6E, MRMSrcReg, (outs FR32:$dst), (ins GR32:$src),
4294 def VMOVZPQILo2PQIrr : I<0x7E, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
4298 def MOVZPQILo2PQIrr : I<0x7E, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
4333 def rr : S3SI<op, MRMSrcReg, (outs RC:$dst), (ins RC:$src),
4397 def rr : S3DI<0x12, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
4411 def rr : S3DI<0x12, MRMSrcReg, (outs VR256:$dst), (ins VR256:$src),
4470 def rr : I<0xD0, MRMSrcReg,
4524 def rr : S3DI<o, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2),
4544 def rr : S3I<o, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2),
4605 def rr : SS38I<opc, MRMSrcReg, (outs VR128:$dst),
4622 def Yrr : SS38I<opc, MRMSrcReg, (outs VR256:$dst),
4674 def rr : SS38I<opc, MRMSrcReg, (outs RC:$dst),
4696 def rr : SS38I<opc, MRMSrcReg, (outs VR128:$dst),
4717 def Yrr : SS38I<opc, MRMSrcReg, (outs VR256:$dst),
4860 def rri : SS3AI<0x0F, MRMSrcReg, (outs RC:$dst),
4925 def rr : SS48I<opc, MRMSrcReg, (outs OutRC:$dst), (ins InRC:$src),
5268 def rr : SS4AIi8<opc, MRMSrcReg, (outs VR128:$dst),
5294 def rr : SS4AIi8<opc, MRMSrcReg, (outs VR128:$dst),
5320 def rr : SS4AIi8<opc, MRMSrcReg, (outs VR128:$dst),
5351 def rr : SS4AIi8<opc, MRMSrcReg, (outs VR128:$dst),
5392 def r : SS4AIi8<opc, MRMSrcReg,
5413 def SSr : SS4AIi8<opcss, MRMSrcReg,
5428 def SDr : SS4AIi8<opcsd, MRMSrcReg,
5447 def SSr : SS4AIi8<opcss, MRMSrcReg,
5462 def SDr : SS4AIi8<opcsd, MRMSrcReg,
5484 def SSr_Int : SS4AIi8<opcss, MRMSrcReg,
5507 def SDr_Int : SS4AIi8<opcsd, MRMSrcReg,
5608 def VPTESTrr : SS48I<0x17, MRMSrcReg, (outs), (ins VR128:$src1, VR128:$src2),
5618 def VPTESTYrr : SS48I<0x17, MRMSrcReg, (outs), (ins VR256:$src1, VR256:$src2),
5630 def PTESTrr : SS48I<0x17, MRMSrcReg, (outs), (ins VR128:$src1, VR128:$src2),
5644 def rr : SS48I<opc, MRMSrcReg, (outs), (ins RC:$src1, RC:$src2),
5674 def POPCNT16rr : I<0xB8, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src),
5684 def POPCNT32rr : I<0xB8, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src),
5695 def POPCNT64rr : RI<0xB8, MRMSrcReg, (outs GR64:$dst), (ins GR64:$src),
5710 def rr : SS48I<opc, MRMSrcReg, (outs VR128:$dst),
5739 def rr : SS48I<opc, MRMSrcReg, (outs RC:$dst),
5872 def rri : SS4AIi8<opc, MRMSrcReg, (outs RC:$dst),
5899 def rri : SS4AIi8<opc, MRMSrcReg, (outs RC:$dst),
6056 def rri : SS4AIi8<opc, MRMSrcReg, (outs RC:$dst),
6202 def rr : Ii8Reg<opc, MRMSrcReg, (outs RC:$dst),
6335 def rr0 : SS48I<opc, MRMSrcReg, (outs VR128:$dst),
6455 def rr : SS428I<opc, MRMSrcReg, (outs RC:$dst),
6491 def rr : SS42AI<0x62, MRMSrcReg, (outs),
6509 def rr : SS42AI<0x60, MRMSrcReg, (outs),
6527 def rr : SS42AI<0x63, MRMSrcReg, (outs),
6545 def rr : SS42AI<0x61, MRMSrcReg, (outs),
6573 SS42FI<opc, MRMSrcReg, (outs RCOut:$dst), (ins RCOut:$src1, RCIn:$src2),
6618 def rr : I<Opc, MRMSrcReg, (outs VR128:$dst),
6642 def SHA1RNDS4rri : Ii8<0xCC, MRMSrcReg, (outs VR128:$dst),
6693 def rr : AES8I<opc, MRMSrcReg, (outs RC:$dst),
6744 def VAESIMCrr : AES8I<0xDB, MRMSrcReg, (outs VR128:$dst),
6756 def AESIMCrr : AES8I<0xDB, MRMSrcReg, (outs VR128:$dst),
6769 def VAESKEYGENASSIST128rr : AESAI<0xDF, MRMSrcReg, (outs VR128:$dst),
6782 def AESKEYGENASSIST128rr : AESAI<0xDF, MRMSrcReg, (outs VR128:$dst),
6809 def PCLMULQDQrr : PCLMULIi8<0x44, MRMSrcReg, (outs VR128:$dst),
6846 def rr : PCLMULIi8<0x44, MRMSrcReg, (outs RC:$dst),
6911 def EXTRQ : I<0x79, MRMSrcReg, (outs VR128:$dst),
6918 def INSERTQI : Ii8<0x78, MRMSrcReg, (outs VR128:$dst),
6924 def INSERTQ : I<0x79, MRMSrcReg, (outs VR128:$dst),
6971 AVX28I<opc, MRMSrcReg, (outs RC:$dst), (ins VR128:$src),
7040 def VINSERTF128rr : AVXAIi8<0x18, MRMSrcReg, (outs VR256:$dst),
7174 def rr : AVX8I<opc, MRMSrcReg, (outs VR128:$dst),
7189 def Yrr : AVX8I<opc, MRMSrcReg, (outs VR256:$dst),
7220 def rr : AVX8I<opc_rm, MRMSrcReg, (outs RC:$dst),
7232 def ri : AVXAIi8<opc_rmi, MRMSrcReg, (outs RC:$dst),
7269 def VPERM2F128rr : AVXAIi8<0x06, MRMSrcReg, (outs VR256:$dst),
7333 def rr : I<0x13, MRMSrcReg, (outs RC:$dst), (ins VR128:$src),
7396 def rri : AVX2AIi8<opc, MRMSrcReg, (outs RC:$dst),
7483 def rr : AVX28I<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
7493 def Yrr : AVX28I<opc, MRMSrcReg, (outs VR256:$dst), (ins VR128:$src),
7622 def Yrr : AVX28I<opc, MRMSrcReg, (outs VR256:$dst),
7648 def Yri : AVX2AIi8<opc, MRMSrcReg, (outs VR256:$dst),
7676 def VPERM2I128rr : AVX2AIi8<0x46, MRMSrcReg, (outs VR256:$dst),
7699 def VINSERTI128rr : AVX2AIi8<0x38, MRMSrcReg, (outs VR256:$dst),
7848 def rr : AVX28I<opc, MRMSrcReg, (outs VR128:$dst),
7862 def Yrr : AVX28I<opc, MRMSrcReg, (outs VR256:$dst),
7949 def rr : PDI<0xCF, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2), "",
7966 def rri : Ii8<Op, MRMSrcReg, (outs RC:$dst),