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Lines Matching refs:YMM

365                                  SSEPackedSingle, SchedWriteFMoveLS.YMM>,
368 SSEPackedDouble, SchedWriteFMoveLS.YMM>,
371 SSEPackedSingle, SchedWriteFMoveLS.YMM>,
374 SSEPackedDouble, SchedWriteFMoveLS.YMM>,
415 let SchedRW = [SchedWriteFMoveLS.YMM.MR] in {
457 let SchedRW = [SchedWriteFMoveLS.YMM.RR] in {
1532 // YMM only
1616 // YMM only
1944 SchedWriteFCmpSizes.PS.YMM, SSEPackedSingle, loadv8f32>, PS, VEX_4V, VEX_L, VEX_WIG;
1947 SchedWriteFCmpSizes.PD.YMM, SSEPackedDouble, loadv4f64>, PD, VEX_4V, VEX_L, VEX_WIG;
2038 loadv8f32, SchedWriteFShuffle.YMM, SSEPackedSingle>,
2046 loadv4f64, SchedWriteFShuffle.YMM, SSEPackedDouble>,
2098 SchedWriteFShuffle.YMM, SSEPackedSingle>, PS, VEX_4V, VEX_L, VEX_WIG;
2101 SchedWriteFShuffle.YMM, SSEPackedDouble>, PD, VEX_4V, VEX_L, VEX_WIG;
2104 SchedWriteFShuffle.YMM, SSEPackedSingle>, PS, VEX_4V, VEX_L, VEX_WIG;
2107 SchedWriteFShuffle.YMM, SSEPackedDouble>, PD, VEX_4V, VEX_L, VEX_WIG;
2243 OpVT256, VR256, load, i256mem, sched.YMM,
2270 !strconcat(OpcodeStr, "ps"), f256mem, sched.YMM,
2274 !strconcat(OpcodeStr, "pd"), f256mem, sched.YMM,
2602 SSEPackedSingle, sched.PS.YMM, 0>, PS, VEX_4V, VEX_L, VEX_WIG;
2605 SSEPackedDouble, sched.PD.YMM, 0>, PD, VEX_4V, VEX_L, VEX_WIG;
2919 VEX, VEX_L, Sched<[sched.YMM]>, VEX_WIG;
2924 VEX, VEX_L, Sched<[sched.YMM.Folded]>, VEX_WIG;
2955 VEX, VEX_L, Sched<[sched.YMM]>, VEX_WIG;
2960 VEX, VEX_L, Sched<[sched.YMM.Folded]>, VEX_WIG;
3078 let SchedRW = [SchedWriteFMoveLSNT.YMM.MR] in {
3103 Sched<[SchedWriteVecMoveLSNT.YMM.MR]>;
3242 Sched<[SchedWriteVecMoveLS.YMM.RR]>, VEX, VEX_L, VEX_WIG;
3245 Sched<[SchedWriteVecMoveLS.YMM.RR]>, VEX, VEX_L, VEX_WIG;
3256 Sched<[SchedWriteVecMoveLS.YMM.RR]>,
3264 Sched<[SchedWriteVecMoveLS.YMM.RR]>,
3276 Sched<[SchedWriteVecMoveLS.YMM.RM]>,
3285 Sched<[SchedWriteVecMoveLS.YMM.RM]>,
3298 Sched<[SchedWriteVecMoveLS.YMM.MR]>, VEX, VEX_L, VEX_WIG;
3305 Sched<[SchedWriteVecMoveLS.YMM.MR]>, XS, VEX, VEX_L, VEX_WIG;
3489 VR256, load, i256mem, SchedWriteVecIMul.YMM,
3501 load, i256mem, SchedWritePSADBW.YMM, 0>,
3555 OpNode, OpNode2, VR256, sched.YMM, schedImm.YMM,
3582 VR256, v32i8, sched.YMM, 0>,
3673 VEX, VEX_L, Sched<[sched.YMM]>, VEX_WIG;
3681 Sched<[sched.YMM.Folded]>, VEX_WIG;
3784 i256mem, SchedWriteShuffle.YMM, load, 0>,
3787 i256mem, SchedWriteShuffle.YMM, load, 0>,
3791 i256mem, SchedWriteShuffle.YMM, load, 0>,
3794 i256mem, SchedWriteShuffle.YMM, load, 0>,
3869 i256mem, SchedWriteShuffle.YMM, load, 0>,
3872 i256mem, SchedWriteShuffle.YMM, load, 0>,
3875 i256mem, SchedWriteShuffle.YMM, load, 0>,
3878 i256mem, SchedWriteShuffle.YMM, load, 0>,
3884 i256mem, SchedWriteShuffle.YMM, load, 0>,
3887 i256mem, SchedWriteShuffle.YMM, load, 0>,
3890 i256mem, SchedWriteShuffle.YMM, load, 0>,
3893 i256mem, SchedWriteShuffle.YMM, load, 0>,
4352 SchedWriteFShuffle.YMM>, VEX, VEX_L, VEX_WIG;
4355 SchedWriteFShuffle.YMM>, VEX, VEX_L, VEX_WIG;
4414 Sched<[sched.YMM]>;
4419 Sched<[sched.YMM.Folded]>;
4454 Sched<[SchedWriteVecMoveLS.YMM.RM]>, VEX, VEX_L, VEX_WIG;
4493 SchedWriteFAddSizes.PS.YMM, loadv8f32, 0>,
4501 SchedWriteFAddSizes.PD.YMM, loadv4f64, 0>,
4626 Sched<[sched.YMM]>;
4633 Sched<[sched.YMM.Folded]>;
4780 SchedWriteVarShuffle.YMM, 0>, VEX_4V, VEX_L, VEX_WIG;
4783 SchedWriteVecIMul.YMM, 0>, VEX_4V, VEX_L, VEX_WIG;
4787 SchedWriteVecIMul.YMM, 0>, VEX_4V, VEX_L, VEX_WIG;
4794 SchedWritePHAdd.YMM, 0>, VEX_4V, VEX_L, VEX_WIG;
4797 SchedWritePHAdd.YMM, 0>, VEX_4V, VEX_L, VEX_WIG;
4800 SchedWritePHAdd.YMM, 0>, VEX_4V, VEX_L, VEX_WIG;
4803 SchedWritePHAdd.YMM, 0>, VEX_4V, VEX_L;
4805 SchedWriteVecALU.YMM>, VEX_4V, VEX_L, VEX_WIG;
4807 SchedWriteVecALU.YMM>, VEX_4V, VEX_L, VEX_WIG;
4809 SchedWriteVecALU.YMM>, VEX_4V, VEX_L, VEX_WIG;
4812 SchedWritePHAdd.YMM>, VEX_4V, VEX_L, VEX_WIG;
4815 SchedWritePHAdd.YMM>, VEX_4V, VEX_L, VEX_WIG;
4887 SchedWriteShuffle.YMM, 0>, VEX_4V, VEX_L, VEX_WIG;
5539 loadv8f32, X86any_VRndScale, SchedWriteFRnd.YMM>,
5548 loadv4f64, X86any_VRndScale, SchedWriteFRnd.YMM>,
5621 Sched<[SchedWriteVecTest.YMM]>, VEX, VEX_L, VEX_WIG;
5625 Sched<[SchedWriteVecTest.YMM.Folded, SchedWriteVecTest.YMM.ReadAfterFold]>,
5659 SchedWriteFTest.YMM>, VEX_L;
5665 SchedWriteFTest.YMM>, VEX_L;
5790 load, i256mem, SchedWriteVecALU.YMM, 0>,
5793 load, i256mem, SchedWriteVecALU.YMM, 0>,
5796 load, i256mem, SchedWriteVecALU.YMM, 0>,
5799 load, i256mem, SchedWriteVecALU.YMM, 0>,
5802 load, i256mem, SchedWriteVecIMul.YMM, 0>,
5807 load, i256mem, SchedWriteVecALU.YMM, 0>,
5810 load, i256mem, SchedWriteVecALU.YMM, 0>,
5813 load, i256mem, SchedWriteVecALU.YMM, 0>,
5816 load, i256mem, SchedWriteVecALU.YMM, 0>,
5852 load, i256mem, SchedWritePMULLD.YMM, 0>,
5856 load, i256mem, SchedWriteVecALU.YMM, 0>,
6020 SchedWriteDPPS.YMM>, VEX_4V, VEX_L, VEX_WIG;
6028 SchedWriteMPSAD.YMM>, VEX_4V, VEX_L, VEX_WIG;
6090 SchedWriteFBlend.YMM, BlendCommuteImm8>,
6098 SchedWriteFBlend.YMM, BlendCommuteImm4>,
6109 SchedWriteBlend.YMM, BlendCommuteImm8>,
6232 SchedWriteFVarBlend.YMM>, VEX_L;
6240 SchedWriteFVarBlend.YMM>, VEX_L;
6250 SchedWriteVarBlend.YMM>, VEX_L;
6394 Sched<[SchedWriteVecMoveLSNT.YMM.RM]>, VEX, VEX_L, VEX_WIG;
6479 load, i256mem, SchedWriteVecALU.YMM, 0>,
7052 // with YMM register containing zero.
7251 v8f32, v8i32, SchedWriteFShuffle.YMM,
7252 SchedWriteFVarShuffle.YMM>, VEX_L;
7259 v4f64, v4i64, SchedWriteFShuffle.YMM,
7260 SchedWriteFVarShuffle.YMM>, VEX_L;
7308 // VZERO - Zero YMM registers
7315 // Zero All YMM registers
7320 // Zero Upper bits of YMM registers
7421 SchedWriteBlend.YMM, VR256, i256mem,
7867 VEX_4V, VEX_L, Sched<[SchedWriteVarVecShift.YMM]>;
7874 VEX_4V, VEX_L, Sched<[SchedWriteVarVecShift.YMM.Folded,
7875 SchedWriteVarVecShift.YMM.ReadAfterFold]>;