Lines Matching refs:CL
18 let Uses = [CL], SchedRW = [WriteShiftCL] in {
21 [(set GR8:$dst, (shl GR8:$src1, CL))]>;
24 [(set GR16:$dst, (shl GR16:$src1, CL))]>, OpSize16;
27 [(set GR32:$dst, (shl GR32:$src1, CL))]>, OpSize32;
30 [(set GR64:$dst, (shl GR64:$src1, CL))]>;
31 } // Uses = [CL], SchedRW
66 // FIXME: Why do we need an explicit "Uses = [CL]" when the instr has a pattern
67 // using CL?
68 let Uses = [CL], SchedRW = [WriteShiftCLLd, WriteRMW] in {
71 [(store (shl (loadi8 addr:$dst), CL), addr:$dst)]>;
74 [(store (shl (loadi16 addr:$dst), CL), addr:$dst)]>,
78 [(store (shl (loadi32 addr:$dst), CL), addr:$dst)]>,
82 [(store (shl (loadi64 addr:$dst), CL), addr:$dst)]>,
122 let Uses = [CL], SchedRW = [WriteShiftCL] in {
125 [(set GR8:$dst, (srl GR8:$src1, CL))]>;
128 [(set GR16:$dst, (srl GR16:$src1, CL))]>, OpSize16;
131 [(set GR32:$dst, (srl GR32:$src1, CL))]>, OpSize32;
134 [(set GR64:$dst, (srl GR64:$src1, CL))]>;
168 let Uses = [CL], SchedRW = [WriteShiftCLLd, WriteRMW] in {
171 [(store (srl (loadi8 addr:$dst), CL), addr:$dst)]>;
174 [(store (srl (loadi16 addr:$dst), CL), addr:$dst)]>,
178 [(store (srl (loadi32 addr:$dst), CL), addr:$dst)]>,
182 [(store (srl (loadi64 addr:$dst), CL), addr:$dst)]>,
222 let Uses = [CL], SchedRW = [WriteShiftCL] in {
225 [(set GR8:$dst, (sra GR8:$src1, CL))]>;
228 [(set GR16:$dst, (sra GR16:$src1, CL))]>,
232 [(set GR32:$dst, (sra GR32:$src1, CL))]>,
236 [(set GR64:$dst, (sra GR64:$src1, CL))]>;
271 let Uses = [CL], SchedRW = [WriteShiftCLLd, WriteRMW] in {
274 [(store (sra (loadi8 addr:$dst), CL), addr:$dst)]>;
277 [(store (sra (loadi16 addr:$dst), CL), addr:$dst)]>,
281 [(store (sra (loadi32 addr:$dst), CL), addr:$dst)]>,
285 [(store (sra (loadi64 addr:$dst), CL), addr:$dst)]>,
331 let Uses = [CL, EFLAGS], SchedRW = [WriteRotateCL] in {
340 } // Uses = [CL, EFLAGS]
361 let Uses = [CL, EFLAGS], SchedRW = [WriteRotateCL] in {
370 } // Uses = [CL, EFLAGS]
432 let Uses = [CL, EFLAGS], SchedRW = [WriteRotateCLLd, WriteRMW] in {
452 } // Uses = [CL, EFLAGS]
458 let Uses = [CL], SchedRW = [WriteRotateCL] in {
461 [(set GR8:$dst, (rotl GR8:$src1, CL))]>;
464 [(set GR16:$dst, (rotl GR16:$src1, CL))]>, OpSize16;
467 [(set GR32:$dst, (rotl GR32:$src1, CL))]>, OpSize32;
470 [(set GR64:$dst, (rotl GR64:$src1, CL))]>;
504 let Uses = [CL], SchedRW = [WriteRotateCLLd, WriteRMW] in {
507 [(store (rotl (loadi8 addr:$dst), CL), addr:$dst)]>;
510 [(store (rotl (loadi16 addr:$dst), CL), addr:$dst)]>, OpSize16;
513 [(store (rotl (loadi32 addr:$dst), CL), addr:$dst)]>, OpSize32;
516 [(store (rotl (loadi64 addr:$dst), CL), addr:$dst)]>,
556 let Uses = [CL], SchedRW = [WriteRotateCL] in {
559 [(set GR8:$dst, (rotr GR8:$src1, CL))]>;
562 [(set GR16:$dst, (rotr GR16:$src1, CL))]>, OpSize16;
565 [(set GR32:$dst, (rotr GR32:$src1, CL))]>, OpSize32;
568 [(set GR64:$dst, (rotr GR64:$src1, CL))]>;
602 let Uses = [CL], SchedRW = [WriteRotateCLLd, WriteRMW] in {
605 [(store (rotr (loadi8 addr:$dst), CL), addr:$dst)]>;
608 [(store (rotr (loadi16 addr:$dst), CL), addr:$dst)]>, OpSize16;
611 [(store (rotr (loadi32 addr:$dst), CL), addr:$dst)]>, OpSize32;
614 [(store (rotr (loadi64 addr:$dst), CL), addr:$dst)]>,
660 let Uses = [CL], SchedRW = [WriteSHDrrcl] in {
664 [(set GR16:$dst, (X86fshl GR16:$src1, GR16:$src2, CL))]>,
669 [(set GR16:$dst, (X86fshr GR16:$src2, GR16:$src1, CL))]>,
674 [(set GR32:$dst, (fshl GR32:$src1, GR32:$src2, CL))]>,
679 [(set GR32:$dst, (fshr GR32:$src2, GR32:$src1, CL))]>,
684 [(set GR64:$dst, (fshl GR64:$src1, GR64:$src2, CL))]>,
689 [(set GR64:$dst, (fshr GR64:$src2, GR64:$src1, CL))]>,
739 let Uses = [CL], SchedRW = [WriteSHDmrcl] in {
742 [(store (X86fshl (loadi16 addr:$dst), GR16:$src2, CL),
746 [(store (X86fshr GR16:$src2, (loadi16 addr:$dst), CL),
751 [(store (fshl (loadi32 addr:$dst), GR32:$src2, CL),
755 [(store (fshr GR32:$src2, (loadi32 addr:$dst), CL),
760 [(store (fshl (loadi64 addr:$dst), GR64:$src2, CL),
764 [(store (fshr GR64:$src2, (loadi64 addr:$dst), CL),