Lines Matching refs:RBI
63 const X86RegisterBankInfo &RBI);
136 const X86RegisterBankInfo &RBI; member in __anon15f3243b0111::X86InstructionSelector
155 const X86RegisterBankInfo &RBI) in X86InstructionSelector() argument
157 TRI(*STI.getRegisterInfo()), RBI(RBI), in X86InstructionSelector()
200 const RegisterBank &RegBank = *RBI.getRegBank(Reg, MRI, TRI); in getRegClass()
235 const unsigned DstSize = RBI.getSizeInBits(DstReg, MRI, TRI); in selectCopy()
236 const RegisterBank &DstRegBank = *RBI.getRegBank(DstReg, MRI, TRI); in selectCopy()
239 const unsigned SrcSize = RBI.getSizeInBits(SrcReg, MRI, TRI); in selectCopy()
240 const RegisterBank &SrcRegBank = *RBI.getRegBank(SrcReg, MRI, TRI); in selectCopy()
275 DstSize <= RBI.getSizeInBits(SrcReg, MRI, TRI))) && in selectCopy()
299 if (!RBI.constrainGenericRegister(DstReg, *DstRC, MRI)) { in selectCopy()
510 const RegisterBank &RB = *RBI.getRegBank(DefReg, MRI, TRI); in selectLoadStoreOp()
548 return constrainSelectedInstRegOperands(I, TII, TRI, RBI); in selectLoadStoreOp()
585 return constrainSelectedInstRegOperands(I, TII, TRI, RBI); in selectFrameIndexOrGep()
631 return constrainSelectedInstRegOperands(I, TII, TRI, RBI); in selectGlobalValue()
643 if (RBI.getRegBank(DefReg, MRI, TRI)->getID() != X86::GPRRegBankID) in selectConstant()
678 return constrainSelectedInstRegOperands(I, TII, TRI, RBI); in selectConstant()
696 if (!RBI.constrainGenericRegister(SrcReg, *SrcRC, MRI) || in selectTurnIntoCOPY()
697 !RBI.constrainGenericRegister(DstReg, *DstRC, MRI)) { in selectTurnIntoCOPY()
719 const RegisterBank &DstRB = *RBI.getRegBank(DstReg, MRI, TRI); in selectTruncOrPtrToInt()
720 const RegisterBank &SrcRB = *RBI.getRegBank(SrcReg, MRI, TRI); in selectTruncOrPtrToInt()
759 if (!RBI.constrainGenericRegister(SrcReg, *SrcRC, MRI) || in selectTruncOrPtrToInt()
760 !RBI.constrainGenericRegister(DstReg, *DstRC, MRI)) { in selectTruncOrPtrToInt()
831 constrainSelectedInstRegOperands(AndInst, TII, TRI, RBI); in selectZext()
848 const RegisterBank &DstRB = *RBI.getRegBank(DstReg, MRI, TRI); in selectAnyext()
849 const RegisterBank &SrcRB = *RBI.getRegBank(SrcReg, MRI, TRI); in selectAnyext()
869 if (!RBI.constrainGenericRegister(SrcReg, *SrcRC, MRI) || in selectAnyext()
870 !RBI.constrainGenericRegister(DstReg, *DstRC, MRI)) { in selectAnyext()
936 constrainSelectedInstRegOperands(CmpInst, TII, TRI, RBI); in selectCmp()
937 constrainSelectedInstRegOperands(SetInst, TII, TRI, RBI); in selectCmp()
984 RBI.constrainGenericRegister( in selectFCmp()
986 *getRegClass(LLT::scalar(8), *RBI.getRegBank(ResultReg, MRI, TRI)), MRI); in selectFCmp()
1003 constrainSelectedInstRegOperands(CmpInst, TII, TRI, RBI); in selectFCmp()
1004 constrainSelectedInstRegOperands(Set1, TII, TRI, RBI); in selectFCmp()
1005 constrainSelectedInstRegOperands(Set2, TII, TRI, RBI); in selectFCmp()
1006 constrainSelectedInstRegOperands(Set3, TII, TRI, RBI); in selectFCmp()
1028 constrainSelectedInstRegOperands(CmpInst, TII, TRI, RBI); in selectFCmp()
1029 constrainSelectedInstRegOperands(Set, TII, TRI, RBI); in selectFCmp()
1064 if (!RBI.constrainGenericRegister(CarryInReg, X86::GR32RegClass, MRI)) in selectUadde()
1085 if (!constrainSelectedInstRegOperands(AddInst, TII, TRI, RBI) || in selectUadde()
1086 !RBI.constrainGenericRegister(CarryOutReg, X86::GR32RegClass, MRI)) in selectUadde()
1147 return constrainSelectedInstRegOperands(I, TII, TRI, RBI); in selectExtract()
1176 if (!RBI.constrainGenericRegister(SrcReg, *SrcRC, MRI) || in emitExtractSubreg()
1177 !RBI.constrainGenericRegister(DstReg, *DstRC, MRI)) { in emitExtractSubreg()
1213 if (!RBI.constrainGenericRegister(SrcReg, *SrcRC, MRI) || in emitInsertSubreg()
1214 !RBI.constrainGenericRegister(DstReg, *DstRC, MRI)) { in emitInsertSubreg()
1281 return constrainSelectedInstRegOperands(I, TII, TRI, RBI); in selectInsert()
1323 const RegisterBank &RegBank = *RBI.getRegBank(DstReg, MRI, TRI); in selectMergeValues()
1373 constrainSelectedInstRegOperands(TestInst, TII, TRI, RBI); in selectCondBranch()
1392 const RegisterBank &RegBank = *RBI.getRegBank(DstReg, MRI, TRI); in materializeFP()
1441 constrainSelectedInstRegOperands(*LoadInst, TII, TRI, RBI); in materializeFP()
1458 if (!RBI.constrainGenericRegister(DstReg, *RC, MRI)) { in selectImplicitDefOrPHI()
1491 const RegisterBank *RegRB = RBI.getRegBank(DstReg, MRI, TRI); in selectDivRem()
1591 if (!RBI.constrainGenericRegister(Op1Reg, *RegRC, MRI) || in selectDivRem()
1592 !RBI.constrainGenericRegister(Op2Reg, *RegRC, MRI) || in selectDivRem()
1593 !RBI.constrainGenericRegister(DstReg, *RegRC, MRI)) { in selectDivRem()
1692 X86RegisterBankInfo &RBI) { in createX86InstructionSelector() argument
1693 return new X86InstructionSelector(TM, Subtarget, RBI); in createX86InstructionSelector()