Lines Matching refs:SRA
306 { ISD::SRA, MVT::v64i8, 4 }, // psrlw, pand, pxor, psubb. in getArithmeticInstrCost()
317 { ISD::SRA, MVT::v2i64, 1 }, in getArithmeticInstrCost()
318 { ISD::SRA, MVT::v4i64, 1 }, in getArithmeticInstrCost()
319 { ISD::SRA, MVT::v8i64, 1 }, in getArithmeticInstrCost()
323 { ISD::SRA, MVT::v64i8, 8 }, // psrlw, pand, pxor, psubb. in getArithmeticInstrCost()
341 { ISD::SRA, MVT::v32i8, 4 }, // psrlw, pand, pxor, psubb. in getArithmeticInstrCost()
343 { ISD::SRA, MVT::v4i64, 4 }, // 2 x psrad + shuffle. in getArithmeticInstrCost()
361 { ISD::SRA, MVT::v16i8, 4 }, // psrlw, pand, pxor, psubb. in getArithmeticInstrCost()
365 { ISD::SRA, MVT::v32i8, 8+2 }, // 2*(psrlw, pand, pxor, psubb) + split. in getArithmeticInstrCost()
496 { ISD::SRA, MVT::v8i16, 1 }, // vpsravw in getArithmeticInstrCost()
500 { ISD::SRA, MVT::v16i16, 1 }, // vpsravw in getArithmeticInstrCost()
504 { ISD::SRA, MVT::v32i16, 1 }, // vpsravw in getArithmeticInstrCost()
515 { ISD::SRA, MVT::v16i16, 1 }, // psraw. in getArithmeticInstrCost()
518 { ISD::SRA, MVT::v32i16, 2 }, // 2*psraw. in getArithmeticInstrCost()
539 { ISD::SRA, MVT::v8i16, 1 }, // psraw. in getArithmeticInstrCost()
540 { ISD::SRA, MVT::v4i32, 1 }, // psrad. in getArithmeticInstrCost()
565 { ISD::SRA, MVT::v64i8, 24 }, // vpblendvb sequence. in getArithmeticInstrCost()
580 { ISD::SRA, MVT::v16i32, 1 }, in getArithmeticInstrCost()
585 { ISD::SRA, MVT::v2i64, 1 }, in getArithmeticInstrCost()
586 { ISD::SRA, MVT::v4i64, 1 }, in getArithmeticInstrCost()
587 { ISD::SRA, MVT::v8i64, 1 }, in getArithmeticInstrCost()
615 { ISD::SRA, MVT::v4i32, 1 }, in getArithmeticInstrCost()
618 { ISD::SRA, MVT::v8i32, 1 }, in getArithmeticInstrCost()
657 { ISD::SRA, MVT::v16i8, 2 }, in getArithmeticInstrCost()
660 { ISD::SRA, MVT::v8i16, 2 }, in getArithmeticInstrCost()
663 { ISD::SRA, MVT::v4i32, 2 }, in getArithmeticInstrCost()
666 { ISD::SRA, MVT::v2i64, 2 }, in getArithmeticInstrCost()
670 { ISD::SRA, MVT::v32i8, 4+2 }, in getArithmeticInstrCost()
673 { ISD::SRA, MVT::v16i16, 4+2 }, in getArithmeticInstrCost()
676 { ISD::SRA, MVT::v8i32, 4+2 }, in getArithmeticInstrCost()
679 { ISD::SRA, MVT::v4i64, 4+2 }, in getArithmeticInstrCost()
687 if ((ShiftISD == ISD::SRL || ShiftISD == ISD::SRA) && in getArithmeticInstrCost()
706 { ISD::SRA, MVT::v16i16, 2+2 }, // 2*psraw + split. in getArithmeticInstrCost()
707 { ISD::SRA, MVT::v8i32, 2+2 }, // 2*psrad + split. in getArithmeticInstrCost()
708 { ISD::SRA, MVT::v2i64, 4 }, // 2*psrad + shuffle. in getArithmeticInstrCost()
709 { ISD::SRA, MVT::v4i64, 8+2 }, // 2*(2*psrad + shuffle) + split. in getArithmeticInstrCost()
717 if (ISD == ISD::SRA && LT.second == MVT::v4i64 && ST->hasAVX2()) in getArithmeticInstrCost()
746 { ISD::SRA, MVT::v32i8, 24 }, // vpblendvb sequence. in getArithmeticInstrCost()
747 { ISD::SRA, MVT::v64i8, 48 }, // 2*vpblendvb sequence. in getArithmeticInstrCost()
748 { ISD::SRA, MVT::v16i16, 10 }, // extend/vpsravd/pack sequence. in getArithmeticInstrCost()
749 { ISD::SRA, MVT::v32i16, 20 }, // 2*extend/vpsravd/pack sequence. in getArithmeticInstrCost()
750 { ISD::SRA, MVT::v2i64, 4 }, // srl/xor/sub sequence. in getArithmeticInstrCost()
751 { ISD::SRA, MVT::v4i64, 4 }, // srl/xor/sub sequence. in getArithmeticInstrCost()
865 { ISD::SRA, MVT::v16i8, 24 }, // pblendvb sequence. in getArithmeticInstrCost()
866 { ISD::SRA, MVT::v32i8, 2*24+2 }, // pblendvb sequence + split. in getArithmeticInstrCost()
867 { ISD::SRA, MVT::v8i16, 14 }, // pblendvb sequence. in getArithmeticInstrCost()
868 { ISD::SRA, MVT::v16i16, 2*14+2 }, // pblendvb sequence + split. in getArithmeticInstrCost()
869 { ISD::SRA, MVT::v4i32, 12 }, // Shift each lane + blend. in getArithmeticInstrCost()
870 { ISD::SRA, MVT::v8i32, 2*12+2 }, // Shift each lane + blend + split. in getArithmeticInstrCost()
894 { ISD::SRA, MVT::v16i8, 54 }, // unpacked cmpgtb sequence. in getArithmeticInstrCost()
895 { ISD::SRA, MVT::v8i16, 32 }, // cmpgtb sequence. in getArithmeticInstrCost()
896 { ISD::SRA, MVT::v4i32, 16 }, // Shift each lane + blend. in getArithmeticInstrCost()
897 { ISD::SRA, MVT::v2i64, 12 }, // srl/xor/sub sequence. in getArithmeticInstrCost()
898 { ISD::SRA, MVT::v4i64, 2*12+2 }, // srl/xor/sub sequence+split. in getArithmeticInstrCost()