Lines Matching refs:UMIN
2339 { ISD::UMIN, MVT::v32i16, 1 }, in getTypeBasedIntrinsicInstrCost()
2340 { ISD::UMIN, MVT::v64i8, 1 }, in getTypeBasedIntrinsicInstrCost()
2385 { ISD::UMIN, MVT::v8i64, 1 }, in getTypeBasedIntrinsicInstrCost()
2386 { ISD::UMIN, MVT::v16i32, 1 }, in getTypeBasedIntrinsicInstrCost()
2387 { ISD::UMIN, MVT::v32i16, 2 }, // FIXME: include split in getTypeBasedIntrinsicInstrCost()
2388 { ISD::UMIN, MVT::v64i8, 2 }, // FIXME: include split in getTypeBasedIntrinsicInstrCost()
2389 { ISD::UMIN, MVT::v4i64, 1 }, in getTypeBasedIntrinsicInstrCost()
2390 { ISD::UMIN, MVT::v2i64, 1 }, in getTypeBasedIntrinsicInstrCost()
2470 { ISD::UMIN, MVT::v8i32, 1 }, in getTypeBasedIntrinsicInstrCost()
2471 { ISD::UMIN, MVT::v16i16, 1 }, in getTypeBasedIntrinsicInstrCost()
2472 { ISD::UMIN, MVT::v32i8, 1 }, in getTypeBasedIntrinsicInstrCost()
2525 { ISD::UMIN, MVT::v8i32, 4 }, // 2 x 128-bit Op + extract/insert in getTypeBasedIntrinsicInstrCost()
2526 { ISD::UMIN, MVT::v16i16, 4 }, // 2 x 128-bit Op + extract/insert in getTypeBasedIntrinsicInstrCost()
2527 { ISD::UMIN, MVT::v32i8, 4 }, // 2 x 128-bit Op + extract/insert in getTypeBasedIntrinsicInstrCost()
2570 { ISD::UMIN, MVT::v4i32, 1 }, in getTypeBasedIntrinsicInstrCost()
2571 { ISD::UMIN, MVT::v8i16, 1 }, in getTypeBasedIntrinsicInstrCost()
2631 { ISD::UMIN, MVT::v8i16, 2 }, in getTypeBasedIntrinsicInstrCost()
2632 { ISD::UMIN, MVT::v16i8, 1 }, in getTypeBasedIntrinsicInstrCost()
2755 ISD = ISD::UMIN; in getTypeBasedIntrinsicInstrCost()
3583 ISD = IsUnsigned ? ISD::UMIN : ISD::SMIN; in getMinMaxCost()
3597 {ISD::UMIN, MVT::v16i8, 1}, in getMinMaxCost()
3602 {ISD::UMIN, MVT::v4i32, 1}, in getMinMaxCost()
3603 {ISD::UMIN, MVT::v8i16, 1}, in getMinMaxCost()
3608 {ISD::UMIN, MVT::v2i64, 3}, // xor+pcmpgtq+blendvpd in getMinMaxCost()
3615 {ISD::UMIN, MVT::v8i32, 3}, in getMinMaxCost()
3617 {ISD::UMIN, MVT::v16i16, 3}, in getMinMaxCost()
3619 {ISD::UMIN, MVT::v32i8, 3}, in getMinMaxCost()
3624 {ISD::UMIN, MVT::v8i32, 1}, in getMinMaxCost()
3626 {ISD::UMIN, MVT::v16i16, 1}, in getMinMaxCost()
3628 {ISD::UMIN, MVT::v32i8, 1}, in getMinMaxCost()
3635 {ISD::UMIN, MVT::v2i64, 1}, in getMinMaxCost()
3637 {ISD::UMIN, MVT::v4i64, 1}, in getMinMaxCost()
3639 {ISD::UMIN, MVT::v8i64, 1}, in getMinMaxCost()
3641 {ISD::UMIN, MVT::v16i32, 1}, in getMinMaxCost()
3646 {ISD::UMIN, MVT::v32i16, 1}, in getMinMaxCost()
3648 {ISD::UMIN, MVT::v64i8, 1}, in getMinMaxCost()
3715 ISD = IsUnsigned ? ISD::UMIN : ISD::SMIN; in getMinMaxReductionCost()
3726 {ISD::UMIN, MVT::v2i16, 5}, // need pxors to use pminsw/pmaxsw in getMinMaxReductionCost()
3727 {ISD::UMIN, MVT::v4i16, 7}, // need pxors to use pminsw/pmaxsw in getMinMaxReductionCost()
3728 {ISD::UMIN, MVT::v8i16, 9}, // need pxors to use pminsw/pmaxsw in getMinMaxReductionCost()
3734 {ISD::UMIN, MVT::v2i16, 5}, // same as sse2 in getMinMaxReductionCost()
3735 {ISD::UMIN, MVT::v4i16, 7}, // same as sse2 in getMinMaxReductionCost()
3737 {ISD::UMIN, MVT::v8i16, 4}, // FIXME: umin is cheaper than umax in getMinMaxReductionCost()
3742 {ISD::UMIN, MVT::v2i8, 3}, // same as sse2 in getMinMaxReductionCost()
3743 {ISD::UMIN, MVT::v4i8, 5}, // same as sse2 in getMinMaxReductionCost()
3744 {ISD::UMIN, MVT::v8i8, 7}, // same as sse2 in getMinMaxReductionCost()
3745 {ISD::UMIN, MVT::v16i8, 6}, // FIXME: umin is cheaper than umax in getMinMaxReductionCost()
3750 {ISD::UMIN, MVT::v16i16, 6}, // FIXME: umin is cheaper than umax in getMinMaxReductionCost()
3752 {ISD::UMIN, MVT::v32i8, 8}, in getMinMaxReductionCost()
3757 {ISD::UMIN, MVT::v32i16, 8}, // FIXME: umin is cheaper than umax in getMinMaxReductionCost()
3759 {ISD::UMIN, MVT::v64i8, 10}, in getMinMaxReductionCost()