Lines Matching refs:v64i8
304 { ISD::SHL, MVT::v64i8, 2 }, // psllw + pand. in getArithmeticInstrCost()
305 { ISD::SRL, MVT::v64i8, 2 }, // psrlw + pand. in getArithmeticInstrCost()
306 { ISD::SRA, MVT::v64i8, 4 }, // psrlw, pand, pxor, psubb. in getArithmeticInstrCost()
321 { ISD::SHL, MVT::v64i8, 4 }, // psllw + pand. in getArithmeticInstrCost()
322 { ISD::SRL, MVT::v64i8, 4 }, // psrlw + pand. in getArithmeticInstrCost()
323 { ISD::SRA, MVT::v64i8, 8 }, // psrlw, pand, pxor, psubb. in getArithmeticInstrCost()
386 { ISD::SDIV, MVT::v64i8, 14 }, // 2*ext+2*pmulhw sequence in getArithmeticInstrCost()
387 { ISD::SREM, MVT::v64i8, 16 }, // 2*ext+2*pmulhw+mul+sub sequence in getArithmeticInstrCost()
388 { ISD::UDIV, MVT::v64i8, 14 }, // 2*ext+2*pmulhw sequence in getArithmeticInstrCost()
389 { ISD::UREM, MVT::v64i8, 16 }, // 2*ext+2*pmulhw+mul+sub sequence in getArithmeticInstrCost()
409 { ISD::SDIV, MVT::v64i8, 28 }, // 4*ext+4*pmulhw sequence in getArithmeticInstrCost()
410 { ISD::SREM, MVT::v64i8, 32 }, // 4*ext+4*pmulhw+mul+sub sequence in getArithmeticInstrCost()
411 { ISD::UDIV, MVT::v64i8, 28 }, // 4*ext+4*pmulhw sequence in getArithmeticInstrCost()
412 { ISD::UREM, MVT::v64i8, 32 }, // 4*ext+4*pmulhw+mul+sub sequence in getArithmeticInstrCost()
563 { ISD::SHL, MVT::v64i8, 11 }, // vpblendvb sequence. in getArithmeticInstrCost()
564 { ISD::SRL, MVT::v64i8, 11 }, // vpblendvb sequence. in getArithmeticInstrCost()
565 { ISD::SRA, MVT::v64i8, 24 }, // vpblendvb sequence. in getArithmeticInstrCost()
567 { ISD::MUL, MVT::v64i8, 11 }, // extend/pmullw/trunc sequence. in getArithmeticInstrCost()
589 { ISD::MUL, MVT::v64i8, 26 }, // extend/pmullw/trunc sequence. in getArithmeticInstrCost()
737 { ISD::SHL, MVT::v64i8, 22 }, // 2*vpblendvb sequence. in getArithmeticInstrCost()
742 { ISD::SRL, MVT::v64i8, 22 }, // 2*vpblendvb sequence. in getArithmeticInstrCost()
747 { ISD::SRA, MVT::v64i8, 48 }, // 2*vpblendvb sequence. in getArithmeticInstrCost()
1099 {TTI::SK_Reverse, MVT::v64i8, 1}, // vpermb in getShuffleCost()
1102 {TTI::SK_PermuteSingleSrc, MVT::v64i8, 1}, // vpermb in getShuffleCost()
1105 {TTI::SK_PermuteTwoSrc, MVT::v64i8, 2}, // vpermt2b in getShuffleCost()
1117 {TTI::SK_Broadcast, MVT::v64i8, 1}, // vpbroadcastb in getShuffleCost()
1121 {TTI::SK_Reverse, MVT::v64i8, 2}, // pshufb + vshufi64x2 in getShuffleCost()
1125 {TTI::SK_PermuteSingleSrc, MVT::v64i8, 8}, // extend to v32i16 in getShuffleCost()
1130 {TTI::SK_PermuteTwoSrc, MVT::v64i8, 19}, // 6 * v32i8 + 1 in getShuffleCost()
1133 {TTI::SK_Select, MVT::v64i8, 1}, // vblendmb in getShuffleCost()
1147 {TTI::SK_Broadcast, MVT::v64i8, 1}, // vpbroadcastb in getShuffleCost()
1184 {TTI::SK_PermuteSingleSrc, MVT::v64i8, 14}, in getShuffleCost()
1186 {TTI::SK_PermuteTwoSrc, MVT::v64i8, 42}, in getShuffleCost()
1189 {TTI::SK_Select, MVT::v64i8, 1}, // vpternlogq in getShuffleCost()
1430 { ISD::SIGN_EXTEND, MVT::v64i8, MVT::v64i1, 1 }, in getCastInstrCost()
1443 { ISD::ZERO_EXTEND, MVT::v64i8, MVT::v64i1, 2 }, in getCastInstrCost()
1457 { ISD::TRUNCATE, MVT::v64i1, MVT::v64i8, 2 }, in getCastInstrCost()
2151 { ISD::SETCC, MVT::v64i8, 1 }, in getCmpSelInstrCost()
2154 { ISD::SELECT, MVT::v64i8, 1 }, in getCmpSelInstrCost()
2169 { ISD::SETCC, MVT::v64i8, 2 }, // FIXME: should probably be 4 in getCmpSelInstrCost()
2172 { ISD::SELECT, MVT::v64i8, 2 }, // FIXME: should be 3 in getCmpSelInstrCost()
2298 { ISD::CTLZ, MVT::v64i8, 20 }, in getTypeBasedIntrinsicInstrCost()
2310 { ISD::ABS, MVT::v64i8, 1 }, in getTypeBasedIntrinsicInstrCost()
2314 { ISD::BITREVERSE, MVT::v64i8, 5 }, in getTypeBasedIntrinsicInstrCost()
2318 { ISD::CTLZ, MVT::v64i8, 17 }, in getTypeBasedIntrinsicInstrCost()
2322 { ISD::CTPOP, MVT::v64i8, 6 }, in getTypeBasedIntrinsicInstrCost()
2326 { ISD::CTTZ, MVT::v64i8, 9 }, in getTypeBasedIntrinsicInstrCost()
2328 { ISD::SADDSAT, MVT::v64i8, 1 }, in getTypeBasedIntrinsicInstrCost()
2330 { ISD::SMAX, MVT::v64i8, 1 }, in getTypeBasedIntrinsicInstrCost()
2332 { ISD::SMIN, MVT::v64i8, 1 }, in getTypeBasedIntrinsicInstrCost()
2334 { ISD::SSUBSAT, MVT::v64i8, 1 }, in getTypeBasedIntrinsicInstrCost()
2336 { ISD::UADDSAT, MVT::v64i8, 1 }, in getTypeBasedIntrinsicInstrCost()
2338 { ISD::UMAX, MVT::v64i8, 1 }, in getTypeBasedIntrinsicInstrCost()
2340 { ISD::UMIN, MVT::v64i8, 1 }, in getTypeBasedIntrinsicInstrCost()
2342 { ISD::USUBSAT, MVT::v64i8, 1 }, in getTypeBasedIntrinsicInstrCost()
2348 { ISD::ABS, MVT::v64i8, 2 }, // FIXME: include split in getTypeBasedIntrinsicInstrCost()
2354 { ISD::BITREVERSE, MVT::v64i8, 10 }, in getTypeBasedIntrinsicInstrCost()
2358 { ISD::CTLZ, MVT::v64i8, 18 }, in getTypeBasedIntrinsicInstrCost()
2362 { ISD::CTPOP, MVT::v64i8, 12 }, in getTypeBasedIntrinsicInstrCost()
2366 { ISD::CTTZ, MVT::v64i8, 18 }, in getTypeBasedIntrinsicInstrCost()
2370 { ISD::SMAX, MVT::v64i8, 2 }, // FIXME: include split in getTypeBasedIntrinsicInstrCost()
2376 { ISD::SMIN, MVT::v64i8, 2 }, // FIXME: include split in getTypeBasedIntrinsicInstrCost()
2382 { ISD::UMAX, MVT::v64i8, 2 }, // FIXME: include split in getTypeBasedIntrinsicInstrCost()
2388 { ISD::UMIN, MVT::v64i8, 2 }, // FIXME: include split in getTypeBasedIntrinsicInstrCost()
2400 { ISD::SADDSAT, MVT::v64i8, 2 }, // FIXME: include split in getTypeBasedIntrinsicInstrCost()
2402 { ISD::SSUBSAT, MVT::v64i8, 2 }, // FIXME: include split in getTypeBasedIntrinsicInstrCost()
2404 { ISD::UADDSAT, MVT::v64i8, 2 }, // FIXME: include split in getTypeBasedIntrinsicInstrCost()
2406 { ISD::USUBSAT, MVT::v64i8, 2 }, // FIXME: include split in getTypeBasedIntrinsicInstrCost()
3647 {ISD::SMIN, MVT::v64i8, 1}, in getMinMaxCost()
3648 {ISD::UMIN, MVT::v64i8, 1}, in getMinMaxCost()
3758 {ISD::SMIN, MVT::v64i8, 10}, in getMinMaxReductionCost()
3759 {ISD::UMIN, MVT::v64i8, 10}, in getMinMaxReductionCost()
4655 {3, MVT::v64i8, 22}, //(load 96i8 and) deinterleave into 3 x 32i8 in getInterleavedMemoryOpCostAVX512()
4709 {3, MVT::v64i8, 26}, // interleave 3 x 64i8 into 96i8 (and store) in getInterleavedMemoryOpCostAVX512()
4714 {4, MVT::v64i8, 24} // interleave 4 x 32i8 into 256i8 (and store) in getInterleavedMemoryOpCostAVX512()