Lines Matching refs:bfloat

5 define arm_aapcs_vfpcc <2 x float> @test_vbfdot_f32(<2 x float> %r, <4 x bfloat> %a, <4 x bfloat> %…
8   %0 = bitcast <4 x bfloat> %a to <8 x i8>
9   %1 = bitcast <4 x bfloat> %b to <8 x i8>
11   ; CHECK: %2 = bitcast <8 x i8> %0 to <4 x bfloat>
12   ; CHECK-NEXT: %3 = bitcast <8 x i8> %1 to <4 x bfloat>
13 …all <2 x float> @llvm.arm.neon.bfdot.v2f32.v4bf16(<2 x float> %r, <4 x bfloat> %2, <4 x bfloat> %3)
17 define <4 x float> @test_vbfdotq_f32(<4 x float> %r, <8 x bfloat> %a, <8 x bfloat> %b) {
20   %0 = bitcast <8 x bfloat> %a to <16 x i8>
21   %1 = bitcast <8 x bfloat> %b to <16 x i8>
23   ; CHECK: %2 = bitcast <16 x i8> %0 to <8 x bfloat>
24   ; CHECK-NEXT: %3 = bitcast <16 x i8> %1 to <8 x bfloat>
25 …all <4 x float> @llvm.arm.neon.bfdot.v4f32.v8bf16(<4 x float> %r, <8 x bfloat> %2, <8 x bfloat> %3)
29 define <4 x float> @test_vbfmmlaq_f32(<4 x float> %r, <8 x bfloat> %a, <8 x bfloat> %b) {
32   %0 = bitcast <8 x bfloat> %a to <16 x i8>
33   %1 = bitcast <8 x bfloat> %b to <16 x i8>
35   ; CHECK: %2 = bitcast <16 x i8> %0 to <8 x bfloat>
36   ; CHECK-NEXT: %3 = bitcast <16 x i8> %1 to <8 x bfloat>
37 …fmmla1.i = call <4 x float> @llvm.arm.neon.bfmmla(<4 x float> %r, <8 x bfloat> %2, <8 x bfloat> %3)
41 define <4 x float> @test_vbfmlalbq_laneq_f32(<4 x float> %r, <8 x bfloat> %a, <8 x bfloat> %b) {
44 …%vecinit35 = shufflevector <8 x bfloat> %b, <8 x bfloat> undef, <8 x i32> <i32 3, i32 3, i32 3, i3…
45   %0 = bitcast <8 x bfloat> %a to <16 x i8>
46   %1 = bitcast <8 x bfloat> %vecinit35 to <16 x i8>
48   ; CHECK: %2 = bitcast <16 x i8> %0 to <8 x bfloat>
49   ; CHECK-NEXT: %3 = bitcast <16 x i8> %1 to <8 x bfloat>
50 …lalb1.i = call <4 x float> @llvm.arm.neon.bfmlalb(<4 x float> %r, <8 x bfloat> %2, <8 x bfloat> %3)
54 define <4 x float> @test_vbfmlaltq_laneq_f32(<4 x float> %r, <8 x bfloat> %a, <8 x bfloat> %b) {
57 …%vecinit35 = shufflevector <8 x bfloat> %b, <8 x bfloat> undef, <8 x i32> <i32 3, i32 3, i32 3, i3…
58   %0 = bitcast <8 x bfloat> %a to <16 x i8>
59   %1 = bitcast <8 x bfloat> %vecinit35 to <16 x i8>
61   ; CHECK: %2 = bitcast <16 x i8> %0 to <8 x bfloat>
62   ; CHECK-NEXT: %3 = bitcast <16 x i8> %1 to <8 x bfloat>
63 …lalt1.i = call <4 x float> @llvm.arm.neon.bfmlalt(<4 x float> %r, <8 x bfloat> %2, <8 x bfloat> %3)
68 …ECK: declare <2 x float> @llvm.arm.neon.bfdot.v2f32.v4bf16(<2 x float>, <4 x bfloat>, <4 x bfloat>)
70 …ECK: declare <4 x float> @llvm.arm.neon.bfdot.v4f32.v8bf16(<4 x float>, <8 x bfloat>, <8 x bfloat>)
72 ; CHECK: declare <4 x float> @llvm.arm.neon.bfmmla(<4 x float>, <8 x bfloat>, <8 x bfloat>)
74 ; CHECK: declare <4 x float> @llvm.arm.neon.bfmlalb(<4 x float>, <8 x bfloat>, <8 x bfloat>)
76 ; CHECK: declare <4 x float> @llvm.arm.neon.bfmlalt(<4 x float>, <8 x bfloat>, <8 x bfloat>)