Lines Matching refs:var3
21 @var3 = common global i32 0, align 4
33 store i32 2, i32* @var3, align 4
49 store i32 2, i32* @var3, align 4
358 ; CHECK: [[GV1:%[0-9]+]]:gpr(p0) = G_GLOBAL_VALUE @var3
375 ; CHECK: [[GV5:%[0-9]+]]:gpr(p0) = G_GLOBAL_VALUE @var3
376 ; CHECK: G_STORE [[C4]](s32), [[GV5]](p0) :: (store 4 into @var3)
391 %7:gpr(p0) = G_GLOBAL_VALUE @var3
402 G_STORE %4(s32), %7(p0) :: (store 4 into @var3)
425 ; CHECK: [[ADRP2:%[0-9]+]]:gpr64(p0) = ADRP target-flags(aarch64-page) @var3
426 …HECK: %addlow3:gpr(p0) = G_ADD_LOW [[ADRP2]](p0), target-flags(aarch64-pageoff, aarch64-nc) @var3
444 ; CHECK: [[ADRP5:%[0-9]+]]:gpr64(p0) = ADRP target-flags(aarch64-page) @var3
445 …D_LOW2:%[0-9]+]]:gpr(p0) = G_ADD_LOW [[ADRP5]](p0), target-flags(aarch64-pageoff, aarch64-nc) @var3
446 ; CHECK: G_STORE [[C4]](s32), [[ADD_LOW2]](p0) :: (store 4 into @var3)
462 %7:gpr64(p0) = ADRP target-flags(aarch64-page) @var3
463 %addlow3:gpr(p0) = G_ADD_LOW %7(p0), target-flags(aarch64-pageoff, aarch64-nc) @var3
474 G_STORE %4(s32), %addlow3(p0) :: (store 4 into @var3)