Lines Matching refs:umin

15 declare i8 @llvm.vector.reduce.umin.v16i8(<16 x i8>)
16 declare i16 @llvm.vector.reduce.umin.v8i16(<8 x i16>)
17 declare i32 @llvm.vector.reduce.umin.v4i32(<4 x i32>)
98   %r = call i8 @llvm.vector.reduce.umin.v16i8(<16 x i8> %arr.load)
106   %r = call i16 @llvm.vector.reduce.umin.v8i16(<8 x i16> %arr.load)
114   %r = call i32 @llvm.vector.reduce.umin.v4i32(<4 x i32> %arr.load)
158 declare i16 @llvm.vector.reduce.umin.v16i16(<16 x i16>)
162 ; CHECK: umin [[V0:v[0-9]+]].8h, {{v[0-9]+}}.8h, {{v[0-9]+}}.8h
165   %r = call i16 @llvm.vector.reduce.umin.v16i16(<16 x i16> %arr.load)
169 declare i32 @llvm.vector.reduce.umin.v16i32(<16 x i32>)
173 ; CHECK: umin v
174 ; CHECK-NEXT: umin v
175 ; CHECK-NEXT: umin [[V0:v[0-9]+]].4s, {{v[0-9]+}}.4s, {{v[0-9]+}}.4s
178   %r = call i32 @llvm.vector.reduce.umin.v16i32(<16 x i32> %arr.load)