Lines Matching refs:DIVISOR

5 ; CHECK:       movi   [[DIVISOR:(v[0-9]+)]].16b, #41
6 ; CHECK-NEXT:  smull2 [[SMULL2:(v[0-9]+)]].8h, v0.16b, [[DIVISOR]].16b
7 ; CHECK-NEXT:  smull  [[SMULL:(v[0-9]+)]].8h, v0.8b, [[DIVISOR]].8b
18 ; CHECK-NEXT:  dup    [[DIVISOR:(v[0-9]+)]].8h, [[TMP]]
19 ; CHECK-NEXT:  smull2 [[SMULL2:(v[0-9]+)]].4s, v0.8h, [[DIVISOR]].8h
20 ; CHECK-NEXT:  smull  [[SMULL:(v[0-9]+)]].4s, v0.4h, [[DIVISOR]].4h
33 ; CHECK-NEXT:  dup    [[DIVISOR:(v[0-9]+)]].4s, [[TMP]]
34 ; CHECK-NEXT:  smull2 [[SMULL2:(v[0-9]+)]].2d, v0.4s, [[DIVISOR]].4s
35 ; CHECK-NEXT:  smull  [[SMULL:(v[0-9]+)]].2d, v0.2s, [[DIVISOR]].2s
45 ; CHECK:       movi   [[DIVISOR:(v[0-9]+)]].16b, #121
46 ; CHECK-NEXT:  umull2 [[UMULL2:(v[0-9]+)]].8h, v0.16b, [[DIVISOR]].16b
47 ; CHECK-NEXT:  umull  [[UMULL:(v[0-9]+)]].8h, v0.8b, [[DIVISOR]].8b
57 ; CHECK-NEXT:  dup    [[DIVISOR:(v[0-9]+)]].8h, [[TMP]]
58 ; CHECK-NEXT:  umull2 [[UMULL2:(v[0-9]+)]].4s, v0.8h, [[DIVISOR]].8h
59 ; CHECK-NEXT:  umull  [[UMULL:(v[0-9]+)]].4s, v0.4h, [[DIVISOR]].4h
72 ; CHECK-NEXT:  dup    [[DIVISOR:(v[0-9]+)]].4s, [[TMP]]
73 ; CHECK-NEXT:  umull2 [[UMULL2:(v[0-9]+)]].2d, v0.4s, [[DIVISOR]].4s
74 ; CHECK-NEXT:  umull  [[UMULL:(v[0-9]+)]].2d, v0.2s, [[DIVISOR]].2s