Lines Matching refs:lo12
25 ; OUTLINE-ATOMICS-NEXT: add x1, x1, :lo12:var8
32 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var8
46 ; OUTLINE-ATOMICS-NEXT: add x1, x1, :lo12:var16
53 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var16
67 ; OUTLINE-ATOMICS-NEXT: add x1, x1, :lo12:var32
74 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var32
88 ; OUTLINE-ATOMICS-NEXT: add x1, x1, :lo12:var64
95 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var64
109 ; OUTLINE-ATOMICS-NEXT: add x1, x1, :lo12:var32
116 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var32
129 ; OUTLINE-ATOMICS-NEXT: add x1, x1, :lo12:var64
136 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var64
149 ; OUTLINE-ATOMICS-NEXT: add x1, x1, :lo12:var8
156 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var8
170 ; OUTLINE-ATOMICS-NEXT: add x1, x1, :lo12:var16
177 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var16
191 ; OUTLINE-ATOMICS-NEXT: add x1, x1, :lo12:var32
198 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var32
212 ; OUTLINE-ATOMICS-NEXT: add x1, x1, :lo12:var64
219 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var64
233 ; OUTLINE-ATOMICS-NEXT: add x1, x1, :lo12:var32
240 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var32
253 ; OUTLINE-ATOMICS-NEXT: add x1, x1, :lo12:var64
260 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var64
273 ; OUTLINE-ATOMICS-NEXT: add x1, x1, :lo12:var8
280 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var8
294 ; OUTLINE-ATOMICS-NEXT: add x1, x1, :lo12:var16
301 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var16
315 ; OUTLINE-ATOMICS-NEXT: add x1, x1, :lo12:var32
322 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var32
336 ; OUTLINE-ATOMICS-NEXT: add x1, x1, :lo12:var64
343 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var64
357 ; OUTLINE-ATOMICS-NEXT: add x1, x1, :lo12:var32
364 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var32
377 ; OUTLINE-ATOMICS-NEXT: add x1, x1, :lo12:var64
384 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var64
396 ; OUTLINE-ATOMICS-NEXT: add x9, x9, :lo12:var8
411 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var8
424 ; OUTLINE-ATOMICS-NEXT: add x9, x9, :lo12:var16
439 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var16
452 ; OUTLINE-ATOMICS-NEXT: add x9, x9, :lo12:var32
466 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var32
479 ; OUTLINE-ATOMICS-NEXT: add x9, x9, :lo12:var64
493 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var64
506 ; OUTLINE-ATOMICS-NEXT: add x8, x8, :lo12:var32
519 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var32
531 ; OUTLINE-ATOMICS-NEXT: add x8, x8, :lo12:var64
544 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var64
556 ; OUTLINE-ATOMICS-NEXT: add x9, x9, :lo12:var8
570 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var8
583 ; OUTLINE-ATOMICS-NEXT: add x9, x9, :lo12:var16
597 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var16
610 ; OUTLINE-ATOMICS-NEXT: add x9, x9, :lo12:var32
624 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var32
637 ; OUTLINE-ATOMICS-NEXT: add x9, x9, :lo12:var64
651 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var64
664 ; OUTLINE-ATOMICS-NEXT: add x8, x8, :lo12:var32
677 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var32
689 ; OUTLINE-ATOMICS-NEXT: add x8, x8, :lo12:var64
702 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var64
714 ; OUTLINE-ATOMICS-NEXT: add x9, x9, :lo12:var8
729 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var8
742 ; OUTLINE-ATOMICS-NEXT: add x9, x9, :lo12:var16
757 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var16
770 ; OUTLINE-ATOMICS-NEXT: add x9, x9, :lo12:var32
784 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var32
797 ; OUTLINE-ATOMICS-NEXT: add x9, x9, :lo12:var64
811 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var64
824 ; OUTLINE-ATOMICS-NEXT: add x8, x8, :lo12:var32
837 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var32
849 ; OUTLINE-ATOMICS-NEXT: add x8, x8, :lo12:var64
862 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var64
874 ; OUTLINE-ATOMICS-NEXT: add x9, x9, :lo12:var8
888 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var8
901 ; OUTLINE-ATOMICS-NEXT: add x9, x9, :lo12:var16
915 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var16
928 ; OUTLINE-ATOMICS-NEXT: add x9, x9, :lo12:var32
942 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var32
955 ; OUTLINE-ATOMICS-NEXT: add x9, x9, :lo12:var64
969 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var64
982 ; OUTLINE-ATOMICS-NEXT: add x8, x8, :lo12:var32
995 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var32
1007 ; OUTLINE-ATOMICS-NEXT: add x8, x8, :lo12:var64
1020 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var64
1033 ; OUTLINE-ATOMICS-NEXT: add x1, x1, :lo12:var8
1040 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var8
1054 ; OUTLINE-ATOMICS-NEXT: add x1, x1, :lo12:var16
1061 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var16
1075 ; OUTLINE-ATOMICS-NEXT: add x1, x1, :lo12:var32
1082 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var32
1096 ; OUTLINE-ATOMICS-NEXT: add x1, x1, :lo12:var64
1103 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var64
1117 ; OUTLINE-ATOMICS-NEXT: add x1, x1, :lo12:var32
1124 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var32
1138 ; OUTLINE-ATOMICS-NEXT: add x1, x1, :lo12:var64
1145 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var64
1159 ; OUTLINE-ATOMICS-NEXT: add x2, x2, :lo12:var8
1168 ; CHECK-NEXT: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var8
1182 ; OUTLINE-ATOMICS-NEXT: add x2, x2, :lo12:var8
1193 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var8
1208 ; OUTLINE-ATOMICS-NEXT: add x2, x2, :lo12:var16
1217 ; CHECK-NEXT: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var16
1231 ; OUTLINE-ATOMICS-NEXT: add x2, x2, :lo12:var16
1242 ; CHECK-NEXT: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var16
1258 ; OUTLINE-ATOMICS-NEXT: add x2, x2, :lo12:var32
1267 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var32
1281 ; OUTLINE-ATOMICS-NEXT: add x2, x2, :lo12:var64
1290 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var64
1304 ; OUTLINE-ATOMICS-NEXT: add x4, x4, :lo12:var128
1313 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var128
1328 ; OUTLINE-ATOMICS-NEXT: add x1, x1, :lo12:var8
1336 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var8
1351 ; OUTLINE-ATOMICS-NEXT: add x1, x1, :lo12:var16
1359 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var16
1374 ; OUTLINE-ATOMICS-NEXT: add x1, x1, :lo12:var32
1382 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var32
1397 ; OUTLINE-ATOMICS-NEXT: add x1, x1, :lo12:var64
1405 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var64
1420 ; OUTLINE-ATOMICS-NEXT: add x1, x1, :lo12:var32
1428 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var32
1443 ; OUTLINE-ATOMICS-NEXT: add x1, x1, :lo12:var64
1451 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var64
1465 ; OUTLINE-ATOMICS-NEXT: add x1, x1, :lo12:var8
1474 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var8
1488 ; OUTLINE-ATOMICS-NEXT: add x1, x1, :lo12:var16
1497 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var16
1511 ; OUTLINE-ATOMICS-NEXT: add x1, x1, :lo12:var32
1520 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var32
1534 ; OUTLINE-ATOMICS-NEXT: add x1, x1, :lo12:var64
1543 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var64
1557 ; OUTLINE-ATOMICS-NEXT: add x1, x1, :lo12:var8
1566 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var8
1579 ; OUTLINE-ATOMICS-NEXT: add x1, x1, :lo12:var16
1588 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var16
1601 ; OUTLINE-ATOMICS-NEXT: add x1, x1, :lo12:var32
1610 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var32
1623 ; OUTLINE-ATOMICS-NEXT: add x1, x1, :lo12:var64
1632 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var64
1646 ; OUTLINE-ATOMICS-NEXT: add x1, x1, :lo12:var8
1654 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var8
1668 ; OUTLINE-ATOMICS-NEXT: add x1, x1, :lo12:var16
1676 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var16
1690 ; OUTLINE-ATOMICS-NEXT: add x1, x1, :lo12:var32
1698 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var32
1712 ; OUTLINE-ATOMICS-NEXT: add x1, x1, :lo12:var64
1720 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var64
1733 ; OUTLINE-ATOMICS-NEXT: add x1, x1, :lo12:var8
1741 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var8
1754 ; OUTLINE-ATOMICS-NEXT: add x1, x1, :lo12:var16
1762 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var16
1775 ; OUTLINE-ATOMICS-NEXT: add x1, x1, :lo12:var32
1783 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var32
1796 ; OUTLINE-ATOMICS-NEXT: add x1, x1, :lo12:var64
1804 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var64
1817 ; OUTLINE-ATOMICS-NEXT: add x1, x1, :lo12:var8
1825 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var8
1837 ; OUTLINE-ATOMICS-NEXT: add x1, x1, :lo12:var16
1845 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var16
1857 ; OUTLINE-ATOMICS-NEXT: add x1, x1, :lo12:var32
1865 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var32
1877 ; OUTLINE-ATOMICS-NEXT: add x1, x1, :lo12:var64
1885 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var64
1898 ; OUTLINE-ATOMICS-NEXT: add x1, x1, :lo12:var32
1906 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var32
1920 ; OUTLINE-ATOMICS-NEXT: add x1, x1, :lo12:var64
1928 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var64
1941 ; OUTLINE-ATOMICS-NEXT: add x1, x1, :lo12:var8
1948 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var8
1962 ; OUTLINE-ATOMICS-NEXT: add x1, x1, :lo12:var16
1969 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var16
1983 ; OUTLINE-ATOMICS-NEXT: add x1, x1, :lo12:var32
1990 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var32
2004 ; OUTLINE-ATOMICS-NEXT: add x1, x1, :lo12:var64
2011 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var64
2025 ; OUTLINE-ATOMICS-NEXT: add x1, x1, :lo12:var32
2032 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var32
2045 ; OUTLINE-ATOMICS-NEXT: add x1, x1, :lo12:var64
2052 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var64
2065 ; OUTLINE-ATOMICS-NEXT: add x1, x1, :lo12:var8
2072 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var8
2086 ; OUTLINE-ATOMICS-NEXT: add x1, x1, :lo12:var16
2093 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var16
2107 ; OUTLINE-ATOMICS-NEXT: add x1, x1, :lo12:var32
2114 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var32
2128 ; OUTLINE-ATOMICS-NEXT: add x1, x1, :lo12:var64
2135 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var64
2149 ; OUTLINE-ATOMICS-NEXT: add x1, x1, :lo12:var32
2156 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var32
2169 ; OUTLINE-ATOMICS-NEXT: add x1, x1, :lo12:var64
2176 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var64
2189 ; OUTLINE-ATOMICS-NEXT: add x1, x1, :lo12:var8
2196 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var8
2210 ; OUTLINE-ATOMICS-NEXT: add x1, x1, :lo12:var16
2217 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var16
2231 ; OUTLINE-ATOMICS-NEXT: add x1, x1, :lo12:var32
2238 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var32
2252 ; OUTLINE-ATOMICS-NEXT: add x1, x1, :lo12:var64
2259 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var64
2273 ; OUTLINE-ATOMICS-NEXT: add x1, x1, :lo12:var32
2280 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var32
2293 ; OUTLINE-ATOMICS-NEXT: add x1, x1, :lo12:var64
2300 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var64
2313 ; OUTLINE-ATOMICS-NEXT: add x1, x1, :lo12:var8
2320 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var8
2334 ; OUTLINE-ATOMICS-NEXT: add x1, x1, :lo12:var16
2341 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var16
2355 ; OUTLINE-ATOMICS-NEXT: add x1, x1, :lo12:var32
2362 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var32
2376 ; OUTLINE-ATOMICS-NEXT: add x1, x1, :lo12:var64
2383 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var64
2397 ; OUTLINE-ATOMICS-NEXT: add x1, x1, :lo12:var32
2404 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var32
2417 ; OUTLINE-ATOMICS-NEXT: add x1, x1, :lo12:var64
2424 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var64
2437 ; OUTLINE-ATOMICS-NEXT: add x1, x1, :lo12:var8
2444 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var8
2458 ; OUTLINE-ATOMICS-NEXT: add x1, x1, :lo12:var16
2465 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var16
2479 ; OUTLINE-ATOMICS-NEXT: add x1, x1, :lo12:var32
2486 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var32
2500 ; OUTLINE-ATOMICS-NEXT: add x1, x1, :lo12:var64
2507 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var64
2521 ; OUTLINE-ATOMICS-NEXT: add x1, x1, :lo12:var32
2528 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var32
2541 ; OUTLINE-ATOMICS-NEXT: add x1, x1, :lo12:var64
2548 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var64
2562 ; OUTLINE-ATOMICS-NEXT: add x1, x1, :lo12:var8
2570 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var8
2584 ; OUTLINE-ATOMICS-NEXT: add x1, x1, :lo12:var16
2592 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var16
2606 ; OUTLINE-ATOMICS-NEXT: add x1, x1, :lo12:var32
2614 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var32
2628 ; OUTLINE-ATOMICS-NEXT: add x1, x1, :lo12:var64
2636 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var64
2650 ; OUTLINE-ATOMICS-NEXT: add x1, x1, :lo12:var32
2658 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var32
2672 ; OUTLINE-ATOMICS-NEXT: add x1, x1, :lo12:var64
2680 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var64
2694 ; OUTLINE-ATOMICS-NEXT: add x1, x1, :lo12:var8
2702 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var8
2716 ; OUTLINE-ATOMICS-NEXT: add x1, x1, :lo12:var16
2724 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var16
2738 ; OUTLINE-ATOMICS-NEXT: add x1, x1, :lo12:var32
2746 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var32
2760 ; OUTLINE-ATOMICS-NEXT: add x1, x1, :lo12:var64
2768 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var64
2782 ; OUTLINE-ATOMICS-NEXT: add x1, x1, :lo12:var32
2790 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var32
2804 ; OUTLINE-ATOMICS-NEXT: add x1, x1, :lo12:var64
2812 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var64
2826 ; OUTLINE-ATOMICS-NEXT: add x1, x1, :lo12:var8
2834 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var8
2848 ; OUTLINE-ATOMICS-NEXT: add x1, x1, :lo12:var16
2856 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var16
2870 ; OUTLINE-ATOMICS-NEXT: add x1, x1, :lo12:var32
2878 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var32
2892 ; OUTLINE-ATOMICS-NEXT: add x1, x1, :lo12:var64
2900 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var64
2914 ; OUTLINE-ATOMICS-NEXT: add x1, x1, :lo12:var32
2922 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var32
2936 ; OUTLINE-ATOMICS-NEXT: add x1, x1, :lo12:var64
2944 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var64
2958 ; OUTLINE-ATOMICS-NEXT: add x1, x1, :lo12:var8
2966 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var8
2980 ; OUTLINE-ATOMICS-NEXT: add x1, x1, :lo12:var16
2988 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var16
3002 ; OUTLINE-ATOMICS-NEXT: add x1, x1, :lo12:var32
3010 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var32
3024 ; OUTLINE-ATOMICS-NEXT: add x1, x1, :lo12:var64
3032 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var64
3046 ; OUTLINE-ATOMICS-NEXT: add x1, x1, :lo12:var32
3054 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var32
3068 ; OUTLINE-ATOMICS-NEXT: add x1, x1, :lo12:var64
3076 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var64
3090 ; OUTLINE-ATOMICS-NEXT: add x1, x1, :lo12:var8
3098 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var8
3112 ; OUTLINE-ATOMICS-NEXT: add x1, x1, :lo12:var16
3120 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var16
3134 ; OUTLINE-ATOMICS-NEXT: add x1, x1, :lo12:var32
3142 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var32
3156 ; OUTLINE-ATOMICS-NEXT: add x1, x1, :lo12:var64
3164 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var64
3178 ; OUTLINE-ATOMICS-NEXT: add x1, x1, :lo12:var32
3186 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var32
3200 ; OUTLINE-ATOMICS-NEXT: add x1, x1, :lo12:var64
3208 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var64
3221 ; OUTLINE-ATOMICS-NEXT: add x2, x2, :lo12:var8
3230 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var8
3244 ; OUTLINE-ATOMICS-NEXT: add x2, x2, :lo12:var16
3253 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var16
3267 ; OUTLINE-ATOMICS-NEXT: add x2, x2, :lo12:var32
3276 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var32
3290 ; OUTLINE-ATOMICS-NEXT: add x2, x2, :lo12:var64
3299 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var64
3313 ; OUTLINE-ATOMICS-NEXT: add x4, x4, :lo12:var128
3322 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var128
3336 ; OUTLINE-ATOMICS-NEXT: add x2, x2, :lo12:var8
3345 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var8
3359 ; OUTLINE-ATOMICS-NEXT: add x2, x2, :lo12:var16
3368 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var16
3382 ; OUTLINE-ATOMICS-NEXT: add x2, x2, :lo12:var32
3391 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var32
3405 ; OUTLINE-ATOMICS-NEXT: add x2, x2, :lo12:var64
3414 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var64
3428 ; OUTLINE-ATOMICS-NEXT: add x4, x4, :lo12:var128
3437 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var128
3451 ; OUTLINE-ATOMICS-NEXT: add x2, x2, :lo12:var8
3460 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var8
3474 ; OUTLINE-ATOMICS-NEXT: add x2, x2, :lo12:var16
3483 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var16
3497 ; OUTLINE-ATOMICS-NEXT: add x2, x2, :lo12:var32
3506 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var32
3520 ; OUTLINE-ATOMICS-NEXT: add x2, x2, :lo12:var64
3529 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var64
3543 ; OUTLINE-ATOMICS-NEXT: add x4, x4, :lo12:var128
3552 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var128
3565 ; OUTLINE-ATOMICS-NEXT: add x9, x9, :lo12:var8
3580 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var8
3593 ; OUTLINE-ATOMICS-NEXT: add x9, x9, :lo12:var16
3608 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var16
3621 ; OUTLINE-ATOMICS-NEXT: add x9, x9, :lo12:var32
3635 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var32
3648 ; OUTLINE-ATOMICS-NEXT: add x9, x9, :lo12:var64
3662 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var64
3675 ; OUTLINE-ATOMICS-NEXT: add x8, x8, :lo12:var32
3688 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var32
3700 ; OUTLINE-ATOMICS-NEXT: add x8, x8, :lo12:var64
3713 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var64
3725 ; OUTLINE-ATOMICS-NEXT: add x9, x9, :lo12:var8
3740 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var8
3753 ; OUTLINE-ATOMICS-NEXT: add x9, x9, :lo12:var16
3768 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var16
3781 ; OUTLINE-ATOMICS-NEXT: add x9, x9, :lo12:var32
3795 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var32
3808 ; OUTLINE-ATOMICS-NEXT: add x9, x9, :lo12:var64
3822 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var64
3835 ; OUTLINE-ATOMICS-NEXT: add x8, x8, :lo12:var32
3848 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var32
3860 ; OUTLINE-ATOMICS-NEXT: add x8, x8, :lo12:var64
3873 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var64
3885 ; OUTLINE-ATOMICS-NEXT: add x9, x9, :lo12:var8
3900 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var8
3913 ; OUTLINE-ATOMICS-NEXT: add x9, x9, :lo12:var16
3928 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var16
3941 ; OUTLINE-ATOMICS-NEXT: add x9, x9, :lo12:var32
3955 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var32
3968 ; OUTLINE-ATOMICS-NEXT: add x9, x9, :lo12:var64
3982 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var64
3995 ; OUTLINE-ATOMICS-NEXT: add x8, x8, :lo12:var32
4008 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var32
4020 ; OUTLINE-ATOMICS-NEXT: add x8, x8, :lo12:var64
4033 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var64
4045 ; OUTLINE-ATOMICS-NEXT: add x9, x9, :lo12:var8
4060 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var8
4073 ; OUTLINE-ATOMICS-NEXT: add x9, x9, :lo12:var16
4088 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var16
4101 ; OUTLINE-ATOMICS-NEXT: add x9, x9, :lo12:var32
4115 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var32
4128 ; OUTLINE-ATOMICS-NEXT: add x9, x9, :lo12:var64
4142 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var64
4155 ; OUTLINE-ATOMICS-NEXT: add x8, x8, :lo12:var32
4168 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var32
4180 ; OUTLINE-ATOMICS-NEXT: add x8, x8, :lo12:var64
4193 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var64
4205 ; OUTLINE-ATOMICS-NEXT: add x9, x9, :lo12:var8
4220 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var8
4233 ; OUTLINE-ATOMICS-NEXT: add x9, x9, :lo12:var16
4248 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var16
4261 ; OUTLINE-ATOMICS-NEXT: add x9, x9, :lo12:var32
4275 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var32
4288 ; OUTLINE-ATOMICS-NEXT: add x9, x9, :lo12:var64
4302 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var64
4315 ; OUTLINE-ATOMICS-NEXT: add x8, x8, :lo12:var32
4328 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var32
4340 ; OUTLINE-ATOMICS-NEXT: add x8, x8, :lo12:var64
4353 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var64
4365 ; OUTLINE-ATOMICS-NEXT: add x9, x9, :lo12:var8
4380 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var8
4393 ; OUTLINE-ATOMICS-NEXT: add x9, x9, :lo12:var16
4408 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var16
4421 ; OUTLINE-ATOMICS-NEXT: add x9, x9, :lo12:var32
4435 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var32
4448 ; OUTLINE-ATOMICS-NEXT: add x9, x9, :lo12:var64
4462 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var64
4475 ; OUTLINE-ATOMICS-NEXT: add x8, x8, :lo12:var32
4488 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var32
4500 ; OUTLINE-ATOMICS-NEXT: add x8, x8, :lo12:var64
4513 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var64
4525 ; OUTLINE-ATOMICS-NEXT: add x9, x9, :lo12:var8
4540 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var8
4553 ; OUTLINE-ATOMICS-NEXT: add x9, x9, :lo12:var16
4568 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var16
4581 ; OUTLINE-ATOMICS-NEXT: add x9, x9, :lo12:var32
4595 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var32
4608 ; OUTLINE-ATOMICS-NEXT: add x9, x9, :lo12:var64
4622 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var64
4635 ; OUTLINE-ATOMICS-NEXT: add x8, x8, :lo12:var32
4648 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var32
4660 ; OUTLINE-ATOMICS-NEXT: add x8, x8, :lo12:var64
4673 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var64
4685 ; OUTLINE-ATOMICS-NEXT: add x9, x9, :lo12:var8
4700 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var8
4713 ; OUTLINE-ATOMICS-NEXT: add x9, x9, :lo12:var16
4728 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var16
4741 ; OUTLINE-ATOMICS-NEXT: add x9, x9, :lo12:var32
4755 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var32
4768 ; OUTLINE-ATOMICS-NEXT: add x9, x9, :lo12:var64
4782 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var64
4795 ; OUTLINE-ATOMICS-NEXT: add x8, x8, :lo12:var32
4808 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var32
4820 ; OUTLINE-ATOMICS-NEXT: add x8, x8, :lo12:var64
4833 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var64
4845 ; OUTLINE-ATOMICS-NEXT: add x9, x9, :lo12:var8
4860 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var8
4873 ; OUTLINE-ATOMICS-NEXT: add x9, x9, :lo12:var16
4888 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var16
4901 ; OUTLINE-ATOMICS-NEXT: add x9, x9, :lo12:var32
4915 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var32
4928 ; OUTLINE-ATOMICS-NEXT: add x9, x9, :lo12:var64
4942 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var64
4955 ; OUTLINE-ATOMICS-NEXT: add x8, x8, :lo12:var32
4968 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var32
4980 ; OUTLINE-ATOMICS-NEXT: add x8, x8, :lo12:var64
4993 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var64
5005 ; OUTLINE-ATOMICS-NEXT: add x9, x9, :lo12:var8
5020 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var8
5033 ; OUTLINE-ATOMICS-NEXT: add x9, x9, :lo12:var16
5048 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var16
5061 ; OUTLINE-ATOMICS-NEXT: add x9, x9, :lo12:var32
5075 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var32
5088 ; OUTLINE-ATOMICS-NEXT: add x9, x9, :lo12:var64
5102 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var64
5115 ; OUTLINE-ATOMICS-NEXT: add x8, x8, :lo12:var32
5128 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var32
5140 ; OUTLINE-ATOMICS-NEXT: add x8, x8, :lo12:var64
5153 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var64
5166 ; OUTLINE-ATOMICS-NEXT: add x1, x1, :lo12:var8
5173 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var8
5187 ; OUTLINE-ATOMICS-NEXT: add x1, x1, :lo12:var16
5194 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var16
5208 ; OUTLINE-ATOMICS-NEXT: add x1, x1, :lo12:var32
5215 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var32
5229 ; OUTLINE-ATOMICS-NEXT: add x1, x1, :lo12:var64
5236 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var64
5250 ; OUTLINE-ATOMICS-NEXT: add x1, x1, :lo12:var32
5257 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var32
5270 ; OUTLINE-ATOMICS-NEXT: add x1, x1, :lo12:var64
5277 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var64
5290 ; OUTLINE-ATOMICS-NEXT: add x1, x1, :lo12:var8
5297 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var8
5311 ; OUTLINE-ATOMICS-NEXT: add x1, x1, :lo12:var16
5318 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var16
5332 ; OUTLINE-ATOMICS-NEXT: add x1, x1, :lo12:var32
5339 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var32
5353 ; OUTLINE-ATOMICS-NEXT: add x1, x1, :lo12:var64
5360 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var64
5374 ; OUTLINE-ATOMICS-NEXT: add x1, x1, :lo12:var32
5381 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var32
5394 ; OUTLINE-ATOMICS-NEXT: add x1, x1, :lo12:var64
5401 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var64
5414 ; OUTLINE-ATOMICS-NEXT: add x1, x1, :lo12:var8
5421 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var8
5435 ; OUTLINE-ATOMICS-NEXT: add x1, x1, :lo12:var16
5442 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var16
5456 ; OUTLINE-ATOMICS-NEXT: add x1, x1, :lo12:var32
5463 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var32
5477 ; OUTLINE-ATOMICS-NEXT: add x1, x1, :lo12:var64
5484 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var64
5498 ; OUTLINE-ATOMICS-NEXT: add x1, x1, :lo12:var32
5505 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var32
5518 ; OUTLINE-ATOMICS-NEXT: add x1, x1, :lo12:var64
5525 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var64
5538 ; OUTLINE-ATOMICS-NEXT: add x1, x1, :lo12:var8
5545 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var8
5559 ; OUTLINE-ATOMICS-NEXT: add x1, x1, :lo12:var16
5566 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var16
5580 ; OUTLINE-ATOMICS-NEXT: add x1, x1, :lo12:var32
5587 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var32
5601 ; OUTLINE-ATOMICS-NEXT: add x1, x1, :lo12:var64
5608 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var64
5622 ; OUTLINE-ATOMICS-NEXT: add x1, x1, :lo12:var32
5629 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var32
5642 ; OUTLINE-ATOMICS-NEXT: add x1, x1, :lo12:var64
5649 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var64
5662 ; OUTLINE-ATOMICS-NEXT: add x1, x1, :lo12:var8
5669 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var8
5683 ; OUTLINE-ATOMICS-NEXT: add x1, x1, :lo12:var16
5690 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var16
5704 ; OUTLINE-ATOMICS-NEXT: add x1, x1, :lo12:var32
5711 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var32
5725 ; OUTLINE-ATOMICS-NEXT: add x1, x1, :lo12:var64
5732 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var64
5746 ; OUTLINE-ATOMICS-NEXT: add x1, x1, :lo12:var32
5753 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var32
5766 ; OUTLINE-ATOMICS-NEXT: add x1, x1, :lo12:var64
5773 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var64
5787 ; OUTLINE-ATOMICS-NEXT: add x1, x1, :lo12:var8
5795 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var8
5810 ; OUTLINE-ATOMICS-NEXT: add x1, x1, :lo12:var16
5818 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var16
5833 ; OUTLINE-ATOMICS-NEXT: add x1, x1, :lo12:var32
5841 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var32
5856 ; OUTLINE-ATOMICS-NEXT: add x1, x1, :lo12:var64
5864 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var64
5879 ; OUTLINE-ATOMICS-NEXT: add x1, x1, :lo12:var32
5887 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var32
5902 ; OUTLINE-ATOMICS-NEXT: add x1, x1, :lo12:var64
5910 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var64
5925 ; OUTLINE-ATOMICS-NEXT: add x1, x1, :lo12:var8
5933 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var8
5948 ; OUTLINE-ATOMICS-NEXT: add x1, x1, :lo12:var16
5956 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var16
5971 ; OUTLINE-ATOMICS-NEXT: add x1, x1, :lo12:var32
5979 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var32
5994 ; OUTLINE-ATOMICS-NEXT: add x1, x1, :lo12:var64
6002 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var64
6017 ; OUTLINE-ATOMICS-NEXT: add x1, x1, :lo12:var32
6025 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var32
6040 ; OUTLINE-ATOMICS-NEXT: add x1, x1, :lo12:var64
6048 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var64
6063 ; OUTLINE-ATOMICS-NEXT: add x1, x1, :lo12:var8
6071 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var8
6086 ; OUTLINE-ATOMICS-NEXT: add x1, x1, :lo12:var16
6094 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var16
6109 ; OUTLINE-ATOMICS-NEXT: add x1, x1, :lo12:var32
6117 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var32
6132 ; OUTLINE-ATOMICS-NEXT: add x1, x1, :lo12:var64
6140 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var64
6155 ; OUTLINE-ATOMICS-NEXT: add x1, x1, :lo12:var32
6163 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var32
6178 ; OUTLINE-ATOMICS-NEXT: add x1, x1, :lo12:var64
6186 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var64
6201 ; OUTLINE-ATOMICS-NEXT: add x1, x1, :lo12:var8
6209 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var8
6224 ; OUTLINE-ATOMICS-NEXT: add x1, x1, :lo12:var16
6232 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var16
6247 ; OUTLINE-ATOMICS-NEXT: add x1, x1, :lo12:var32
6255 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var32
6270 ; OUTLINE-ATOMICS-NEXT: add x1, x1, :lo12:var64
6278 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var64
6293 ; OUTLINE-ATOMICS-NEXT: add x1, x1, :lo12:var32
6301 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var32
6316 ; OUTLINE-ATOMICS-NEXT: add x1, x1, :lo12:var64
6324 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var64
6339 ; OUTLINE-ATOMICS-NEXT: add x1, x1, :lo12:var8
6347 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var8
6362 ; OUTLINE-ATOMICS-NEXT: add x1, x1, :lo12:var16
6370 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var16
6385 ; OUTLINE-ATOMICS-NEXT: add x1, x1, :lo12:var32
6393 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var32
6408 ; OUTLINE-ATOMICS-NEXT: add x1, x1, :lo12:var64
6416 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var64
6431 ; OUTLINE-ATOMICS-NEXT: add x1, x1, :lo12:var32
6439 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var32
6454 ; OUTLINE-ATOMICS-NEXT: add x1, x1, :lo12:var64
6462 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var64
6476 ; OUTLINE-ATOMICS-NEXT: add x1, x1, :lo12:var8
6483 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var8
6497 ; OUTLINE-ATOMICS-NEXT: add x1, x1, :lo12:var16
6504 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var16
6518 ; OUTLINE-ATOMICS-NEXT: add x1, x1, :lo12:var32
6525 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var32
6539 ; OUTLINE-ATOMICS-NEXT: add x1, x1, :lo12:var64
6546 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var64
6560 ; OUTLINE-ATOMICS-NEXT: add x1, x1, :lo12:var32
6567 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var32
6581 ; OUTLINE-ATOMICS-NEXT: add x1, x1, :lo12:var64
6588 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var64
6602 ; OUTLINE-ATOMICS-NEXT: add x1, x1, :lo12:var8
6609 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var8
6623 ; OUTLINE-ATOMICS-NEXT: add x1, x1, :lo12:var16
6630 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var16
6644 ; OUTLINE-ATOMICS-NEXT: add x1, x1, :lo12:var32
6651 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var32
6665 ; OUTLINE-ATOMICS-NEXT: add x1, x1, :lo12:var64
6672 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var64
6686 ; OUTLINE-ATOMICS-NEXT: add x1, x1, :lo12:var32
6693 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var32
6707 ; OUTLINE-ATOMICS-NEXT: add x1, x1, :lo12:var64
6714 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var64
6728 ; OUTLINE-ATOMICS-NEXT: add x1, x1, :lo12:var8
6735 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var8
6749 ; OUTLINE-ATOMICS-NEXT: add x1, x1, :lo12:var16
6756 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var16
6770 ; OUTLINE-ATOMICS-NEXT: add x1, x1, :lo12:var32
6777 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var32
6791 ; OUTLINE-ATOMICS-NEXT: add x1, x1, :lo12:var64
6798 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var64
6812 ; OUTLINE-ATOMICS-NEXT: add x1, x1, :lo12:var32
6819 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var32
6833 ; OUTLINE-ATOMICS-NEXT: add x1, x1, :lo12:var64
6840 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var64
6854 ; OUTLINE-ATOMICS-NEXT: add x1, x1, :lo12:var8
6861 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var8
6875 ; OUTLINE-ATOMICS-NEXT: add x1, x1, :lo12:var16
6882 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var16
6896 ; OUTLINE-ATOMICS-NEXT: add x1, x1, :lo12:var32
6903 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var32
6917 ; OUTLINE-ATOMICS-NEXT: add x1, x1, :lo12:var64
6924 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var64
6938 ; OUTLINE-ATOMICS-NEXT: add x1, x1, :lo12:var32
6945 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var32
6959 ; OUTLINE-ATOMICS-NEXT: add x1, x1, :lo12:var64
6966 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var64
6980 ; OUTLINE-ATOMICS-NEXT: add x1, x1, :lo12:var8
6987 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var8
7001 ; OUTLINE-ATOMICS-NEXT: add x1, x1, :lo12:var16
7008 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var16
7022 ; OUTLINE-ATOMICS-NEXT: add x1, x1, :lo12:var32
7029 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var32
7043 ; OUTLINE-ATOMICS-NEXT: add x1, x1, :lo12:var64
7050 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var64
7064 ; OUTLINE-ATOMICS-NEXT: add x1, x1, :lo12:var32
7071 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var32
7085 ; OUTLINE-ATOMICS-NEXT: add x1, x1, :lo12:var64
7092 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var64
7105 ; OUTLINE-ATOMICS-NEXT: add x9, x9, :lo12:var8
7119 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var8
7132 ; OUTLINE-ATOMICS-NEXT: add x9, x9, :lo12:var16
7146 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var16
7159 ; OUTLINE-ATOMICS-NEXT: add x9, x9, :lo12:var32
7173 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var32
7186 ; OUTLINE-ATOMICS-NEXT: add x9, x9, :lo12:var64
7200 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var64
7213 ; OUTLINE-ATOMICS-NEXT: add x8, x8, :lo12:var32
7226 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var32
7238 ; OUTLINE-ATOMICS-NEXT: add x8, x8, :lo12:var64
7251 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var64
7263 ; OUTLINE-ATOMICS-NEXT: add x9, x9, :lo12:var8
7277 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var8
7290 ; OUTLINE-ATOMICS-NEXT: add x9, x9, :lo12:var16
7304 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var16
7317 ; OUTLINE-ATOMICS-NEXT: add x9, x9, :lo12:var32
7331 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var32
7344 ; OUTLINE-ATOMICS-NEXT: add x9, x9, :lo12:var64
7358 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var64
7371 ; OUTLINE-ATOMICS-NEXT: add x8, x8, :lo12:var32
7384 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var32
7396 ; OUTLINE-ATOMICS-NEXT: add x8, x8, :lo12:var64
7409 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var64
7421 ; OUTLINE-ATOMICS-NEXT: add x9, x9, :lo12:var8
7435 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var8
7448 ; OUTLINE-ATOMICS-NEXT: add x9, x9, :lo12:var16
7462 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var16
7475 ; OUTLINE-ATOMICS-NEXT: add x9, x9, :lo12:var32
7489 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var32
7502 ; OUTLINE-ATOMICS-NEXT: add x9, x9, :lo12:var64
7516 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var64
7529 ; OUTLINE-ATOMICS-NEXT: add x8, x8, :lo12:var32
7542 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var32
7554 ; OUTLINE-ATOMICS-NEXT: add x8, x8, :lo12:var64
7567 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var64
7579 ; OUTLINE-ATOMICS-NEXT: add x9, x9, :lo12:var8
7593 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var8
7606 ; OUTLINE-ATOMICS-NEXT: add x9, x9, :lo12:var16
7620 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var16
7633 ; OUTLINE-ATOMICS-NEXT: add x9, x9, :lo12:var32
7647 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var32
7660 ; OUTLINE-ATOMICS-NEXT: add x9, x9, :lo12:var64
7674 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var64
7687 ; OUTLINE-ATOMICS-NEXT: add x8, x8, :lo12:var32
7700 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var32
7712 ; OUTLINE-ATOMICS-NEXT: add x8, x8, :lo12:var64
7725 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var64
7737 ; OUTLINE-ATOMICS-NEXT: add x9, x9, :lo12:var8
7751 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var8
7764 ; OUTLINE-ATOMICS-NEXT: add x9, x9, :lo12:var16
7778 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var16
7791 ; OUTLINE-ATOMICS-NEXT: add x9, x9, :lo12:var32
7805 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var32
7818 ; OUTLINE-ATOMICS-NEXT: add x9, x9, :lo12:var64
7832 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var64
7845 ; OUTLINE-ATOMICS-NEXT: add x8, x8, :lo12:var32
7858 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var32
7870 ; OUTLINE-ATOMICS-NEXT: add x8, x8, :lo12:var64
7883 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var64
7895 ; OUTLINE-ATOMICS-NEXT: add x9, x9, :lo12:var8
7909 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var8
7922 ; OUTLINE-ATOMICS-NEXT: add x9, x9, :lo12:var16
7936 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var16
7949 ; OUTLINE-ATOMICS-NEXT: add x9, x9, :lo12:var32
7963 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var32
7976 ; OUTLINE-ATOMICS-NEXT: add x9, x9, :lo12:var64
7990 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var64
8003 ; OUTLINE-ATOMICS-NEXT: add x8, x8, :lo12:var32
8016 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var32
8028 ; OUTLINE-ATOMICS-NEXT: add x8, x8, :lo12:var64
8041 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var64
8053 ; OUTLINE-ATOMICS-NEXT: add x9, x9, :lo12:var8
8067 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var8
8080 ; OUTLINE-ATOMICS-NEXT: add x9, x9, :lo12:var16
8094 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var16
8107 ; OUTLINE-ATOMICS-NEXT: add x9, x9, :lo12:var32
8121 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var32
8134 ; OUTLINE-ATOMICS-NEXT: add x9, x9, :lo12:var64
8148 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var64
8161 ; OUTLINE-ATOMICS-NEXT: add x8, x8, :lo12:var32
8174 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var32
8186 ; OUTLINE-ATOMICS-NEXT: add x8, x8, :lo12:var64
8199 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var64
8211 ; OUTLINE-ATOMICS-NEXT: add x9, x9, :lo12:var8
8225 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var8
8238 ; OUTLINE-ATOMICS-NEXT: add x9, x9, :lo12:var16
8252 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var16
8265 ; OUTLINE-ATOMICS-NEXT: add x9, x9, :lo12:var32
8279 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var32
8292 ; OUTLINE-ATOMICS-NEXT: add x9, x9, :lo12:var64
8306 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var64
8319 ; OUTLINE-ATOMICS-NEXT: add x8, x8, :lo12:var32
8332 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var32
8344 ; OUTLINE-ATOMICS-NEXT: add x8, x8, :lo12:var64
8357 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var64
8369 ; OUTLINE-ATOMICS-NEXT: add x9, x9, :lo12:var8
8383 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var8
8396 ; OUTLINE-ATOMICS-NEXT: add x9, x9, :lo12:var16
8410 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var16
8423 ; OUTLINE-ATOMICS-NEXT: add x9, x9, :lo12:var32
8437 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var32
8450 ; OUTLINE-ATOMICS-NEXT: add x9, x9, :lo12:var64
8464 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var64
8477 ; OUTLINE-ATOMICS-NEXT: add x8, x8, :lo12:var32
8490 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var32
8502 ; OUTLINE-ATOMICS-NEXT: add x8, x8, :lo12:var64
8515 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var64
8527 ; OUTLINE-ATOMICS-NEXT: add x9, x9, :lo12:var8
8541 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var8
8554 ; OUTLINE-ATOMICS-NEXT: add x9, x9, :lo12:var16
8568 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var16
8581 ; OUTLINE-ATOMICS-NEXT: add x9, x9, :lo12:var32
8595 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var32
8608 ; OUTLINE-ATOMICS-NEXT: add x9, x9, :lo12:var64
8622 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var64
8635 ; OUTLINE-ATOMICS-NEXT: add x8, x8, :lo12:var32
8648 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var32
8660 ; OUTLINE-ATOMICS-NEXT: add x8, x8, :lo12:var64
8673 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var64
8686 ; OUTLINE-ATOMICS-NEXT: add x1, x1, :lo12:var8
8693 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var8
8707 ; OUTLINE-ATOMICS-NEXT: add x1, x1, :lo12:var16
8714 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var16
8728 ; OUTLINE-ATOMICS-NEXT: add x1, x1, :lo12:var32
8735 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var32
8749 ; OUTLINE-ATOMICS-NEXT: add x1, x1, :lo12:var64
8756 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var64
8770 ; OUTLINE-ATOMICS-NEXT: add x1, x1, :lo12:var32
8777 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var32
8790 ; OUTLINE-ATOMICS-NEXT: add x1, x1, :lo12:var64
8797 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var64
8810 ; OUTLINE-ATOMICS-NEXT: add x1, x1, :lo12:var8
8817 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var8
8831 ; OUTLINE-ATOMICS-NEXT: add x1, x1, :lo12:var16
8838 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var16
8852 ; OUTLINE-ATOMICS-NEXT: add x1, x1, :lo12:var32
8859 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var32
8873 ; OUTLINE-ATOMICS-NEXT: add x1, x1, :lo12:var64
8880 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var64
8894 ; OUTLINE-ATOMICS-NEXT: add x1, x1, :lo12:var32
8901 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var32
8914 ; OUTLINE-ATOMICS-NEXT: add x1, x1, :lo12:var64
8921 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var64
8934 ; OUTLINE-ATOMICS-NEXT: add x1, x1, :lo12:var8
8941 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var8
8955 ; OUTLINE-ATOMICS-NEXT: add x1, x1, :lo12:var16
8962 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var16
8976 ; OUTLINE-ATOMICS-NEXT: add x1, x1, :lo12:var32
8983 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var32
8997 ; OUTLINE-ATOMICS-NEXT: add x1, x1, :lo12:var64
9004 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var64
9018 ; OUTLINE-ATOMICS-NEXT: add x1, x1, :lo12:var32
9025 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var32
9038 ; OUTLINE-ATOMICS-NEXT: add x1, x1, :lo12:var64
9045 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var64
9058 ; OUTLINE-ATOMICS-NEXT: add x1, x1, :lo12:var8
9065 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var8
9079 ; OUTLINE-ATOMICS-NEXT: add x1, x1, :lo12:var16
9086 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var16
9100 ; OUTLINE-ATOMICS-NEXT: add x1, x1, :lo12:var32
9107 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var32
9121 ; OUTLINE-ATOMICS-NEXT: add x1, x1, :lo12:var64
9128 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var64
9142 ; OUTLINE-ATOMICS-NEXT: add x1, x1, :lo12:var32
9149 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var32
9162 ; OUTLINE-ATOMICS-NEXT: add x1, x1, :lo12:var64
9169 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var64
9182 ; OUTLINE-ATOMICS-NEXT: add x1, x1, :lo12:var8
9189 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var8
9203 ; OUTLINE-ATOMICS-NEXT: add x1, x1, :lo12:var16
9210 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var16
9224 ; OUTLINE-ATOMICS-NEXT: add x1, x1, :lo12:var32
9231 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var32
9245 ; OUTLINE-ATOMICS-NEXT: add x1, x1, :lo12:var64
9252 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var64
9266 ; OUTLINE-ATOMICS-NEXT: add x1, x1, :lo12:var32
9273 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var32
9286 ; OUTLINE-ATOMICS-NEXT: add x1, x1, :lo12:var64
9293 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var64