Lines Matching refs:lo12

22 ; OUTLINE_ATOMICS-NEXT:    add x1, x1, :lo12:var8
29 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var8
50 ; OUTLINE_ATOMICS-NEXT:    add x1, x1, :lo12:var16
57 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var16
78 ; OUTLINE_ATOMICS-NEXT:    add x1, x1, :lo12:var32
85 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var32
106 ; OUTLINE_ATOMICS-NEXT:    add x1, x1, :lo12:var64
113 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var64
135 ; OUTLINE_ATOMICS-NEXT:    add x1, x1, :lo12:var8
142 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var8
164 ; OUTLINE_ATOMICS-NEXT:    add x1, x1, :lo12:var16
171 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var16
193 ; OUTLINE_ATOMICS-NEXT:    add x1, x1, :lo12:var32
200 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var32
222 ; OUTLINE_ATOMICS-NEXT:    add x1, x1, :lo12:var64
229 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var64
251 ; OUTLINE_ATOMICS-NEXT:    add x1, x1, :lo12:var8
258 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var8
280 ; OUTLINE_ATOMICS-NEXT:    add x1, x1, :lo12:var16
287 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var16
309 ; OUTLINE_ATOMICS-NEXT:    add x1, x1, :lo12:var32
316 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var32
338 ; OUTLINE_ATOMICS-NEXT:    add x1, x1, :lo12:var64
345 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var64
366 ; OUTLINE_ATOMICS-NEXT:    add x1, x1, :lo12:var8
373 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var8
394 ; OUTLINE_ATOMICS-NEXT:    add x1, x1, :lo12:var16
401 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var16
422 ; OUTLINE_ATOMICS-NEXT:    add x1, x1, :lo12:var32
429 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var32
450 ; OUTLINE_ATOMICS-NEXT:    add x1, x1, :lo12:var64
457 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var64
478 ; OUTLINE_ATOMICS-NEXT:    add x1, x1, :lo12:var8
485 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var8
506 ; OUTLINE_ATOMICS-NEXT:    add x1, x1, :lo12:var16
513 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var16
534 ; OUTLINE_ATOMICS-NEXT:    add x1, x1, :lo12:var32
541 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var32
562 ; OUTLINE_ATOMICS-NEXT:    add x1, x1, :lo12:var64
569 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var64
590 ; OUTLINE_ATOMICS-NEXT:    add x1, x1, :lo12:var8
597 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var8
617 ; OUTLINE_ATOMICS-NEXT:    add x1, x1, :lo12:var16
624 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var16
645 ; OUTLINE_ATOMICS-NEXT:    add x1, x1, :lo12:var32
652 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var32
670 ; OUTLINE_ATOMICS-NEXT:    add x1, x1, :lo12:var64
677 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var64
697 ; OUTLINE_ATOMICS-NEXT:    add x9, x9, :lo12:var8
712 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var8
736 ; OUTLINE_ATOMICS-NEXT:    add x9, x9, :lo12:var16
751 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var16
776 ; OUTLINE_ATOMICS-NEXT:    add x9, x9, :lo12:var32
790 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var32
814 ; OUTLINE_ATOMICS-NEXT:    add x9, x9, :lo12:var64
828 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var64
852 ; OUTLINE_ATOMICS-NEXT:    add x9, x9, :lo12:var8
867 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var8
892 ; OUTLINE_ATOMICS-NEXT:    add x9, x9, :lo12:var16
907 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var16
932 ; OUTLINE_ATOMICS-NEXT:    add x9, x9, :lo12:var32
946 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var32
970 ; OUTLINE_ATOMICS-NEXT:    add x9, x9, :lo12:var64
984 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var64
1008 ; OUTLINE_ATOMICS-NEXT:    add x9, x9, :lo12:var8
1022 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var8
1046 ; OUTLINE_ATOMICS-NEXT:    add x9, x9, :lo12:var16
1060 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var16
1084 ; OUTLINE_ATOMICS-NEXT:    add x9, x9, :lo12:var32
1098 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var32
1122 ; OUTLINE_ATOMICS-NEXT:    add x9, x9, :lo12:var64
1136 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var64
1160 ; OUTLINE_ATOMICS-NEXT:    add x9, x9, :lo12:var8
1174 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var8
1198 ; OUTLINE_ATOMICS-NEXT:    add x9, x9, :lo12:var16
1212 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var16
1236 ; OUTLINE_ATOMICS-NEXT:    add x9, x9, :lo12:var32
1250 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var32
1274 ; OUTLINE_ATOMICS-NEXT:    add x9, x9, :lo12:var64
1288 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var64
1313 ; OUTLINE_ATOMICS-NEXT:    add x2, x2, :lo12:var8
1322 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var8
1346 ; OUTLINE_ATOMICS-NEXT:    add x2, x2, :lo12:var16
1355 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var16
1379 ; OUTLINE_ATOMICS-NEXT:    add x2, x2, :lo12:var32
1390 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var32
1410 ; OUTLINE_ATOMICS-NEXT:    add x19, x19, :lo12:var64
1421 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var64
1446 ; OUTLINE_ATOMICS-NEXT:    ldrb w0, [x8, :lo12:var8]
1451 ; CHECK: ldrb w0, [x[[HIADDR]], {{#?}}:lo12:var8]
1479 ; OUTLINE_ATOMICS-NEXT:    add x8, x8, :lo12:var8
1486 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var8
1498 ; OUTLINE_ATOMICS-NEXT:    add x8, x8, :lo12:var8
1505 ; CHECK: add x[[ADDR:[0-9]+]], [[HIADDR]], {{#?}}:lo12:var8
1517 ; OUTLINE_ATOMICS-NEXT:    ldrh w0, [x8, :lo12:var16]
1523 ; CHECK: ldrh w0, [x[[HIADDR]], {{#?}}:lo12:var16]
1551 ; OUTLINE_ATOMICS-NEXT:    add x8, x8, :lo12:var64
1558 ; CHECK: add x[[ADDR:[0-9]+]], [[HIADDR]], {{#?}}:lo12:var64
1570 ; OUTLINE_ATOMICS-NEXT:    strb w0, [x8, :lo12:var8]
1574 ; CHECK: strb w0, [x[[HIADDR]], {{#?}}:lo12:var8]
1598 ; OUTLINE_ATOMICS-NEXT:    add x8, x8, :lo12:var8
1605 ; CHECK: add x[[ADDR:[0-9]+]], [[HIADDR]], {{#?}}:lo12:var8
1617 ; OUTLINE_ATOMICS-NEXT:    add x8, x8, :lo12:var8
1624 ; CHECK: add x[[ADDR:[0-9]+]], [[HIADDR]], {{#?}}:lo12:var8
1637 ; OUTLINE_ATOMICS-NEXT:    strh w0, [x8, :lo12:var16]
1643 ; CHECK: strh w0, [x[[HIADDR]], {{#?}}:lo12:var16]
1670 ; OUTLINE_ATOMICS-NEXT:    add x8, x8, :lo12:var64
1677 ; CHECK: add x[[ADDR:[0-9]+]], [[HIADDR]], {{#?}}:lo12:var64