Lines Matching refs:RDX

254 ; CHECK-NEXT: faddv [[RDX:h[0-9]+]], [[PG]], z1.h
255 ; CHECK-NEXT: fadd h0, h0, [[RDX]]
265 ; CHECK-NEXT: faddv [[RDX:h[0-9]+]], [[PG]], z1.h
266 ; CHECK-NEXT: fadd h0, h0, [[RDX]]
276 ; CHECK-NEXT: faddv [[RDX:h[0-9]+]], [[PG]], [[OP]].h
277 ; CHECK-NEXT: fadd h0, h0, [[RDX]]
288 ; VBITS_GE_512-NEXT: faddv [[RDX:h[0-9]+]], [[PG]], [[OP]].h
289 ; VBITS_GE_512-NEXT: fadd h0, h0, [[RDX]]
299 ; VBITS_EQ_256-DAG: fadd h0, h0, [[RDX]]
310 ; VBITS_GE_1024-NEXT: faddv [[RDX:h[0-9]+]], [[PG]], [[OP]].h
311 ; VBITS_GE_1024-NEXT: fadd h0, h0, [[RDX]]
322 ; VBITS_GE_2048-NEXT: faddv [[RDX:h[0-9]+]], [[PG]], [[OP]].h
323 ; VBITS_GE_2048-NEXT: fadd h0, h0, [[RDX]]
344 ; CHECK-NEXT: faddv [[RDX:s[0-9]+]], [[PG]], z1.s
345 ; CHECK-NEXT: fadd s0, s0, [[RDX]]
355 ; CHECK-NEXT: faddv [[RDX:s[0-9]+]], [[PG]], [[OP]].s
356 ; CHECK-NEXT: fadd s0, s0, [[RDX]]
367 ; VBITS_GE_512-NEXT: faddv [[RDX:s[0-9]+]], [[PG]], [[OP]].s
368 ; VBITS_GE_512-NEXT: fadd s0, s0, [[RDX]]
377 ; VBITS_EQ_256-DAG: faddv [[RDX:s[0-9]+]], [[PG]], [[ADD]].s
378 ; VBITS_EQ_256-DAG: fadd s0, s0, [[RDX]]
389 ; VBITS_GE_1024-NEXT: faddv [[RDX:s[0-9]+]], [[PG]], [[OP]].s
390 ; VBITS_GE_1024-NEXT: fadd s0, s0, [[RDX]]
401 ; VBITS_GE_2048-NEXT: faddv [[RDX:s[0-9]+]], [[PG]], [[OP]].s
402 ; VBITS_GE_2048-NEXT: fadd s0, s0, [[RDX]]
432 ; CHECK-NEXT: faddv [[RDX:d[0-9]+]], [[PG]], [[OP]].d
433 ; CHECK-NEXT: fadd d0, d0, [[RDX]]
444 ; VBITS_GE_512-NEXT: faddv [[RDX:d[0-9]+]], [[PG]], [[OP]].d
445 ; VBITS_GE_512-NEXT: fadd d0, d0, [[RDX]]
454 ; VBITS_EQ_256-DAG: faddv [[RDX:d[0-9]+]], [[PG]], [[ADD]].d
455 ; VBITS_EQ_256-DAG: fadd d0, d0, [[RDX]]
466 ; VBITS_GE_1024-NEXT: faddv [[RDX:d[0-9]+]], [[PG]], [[OP]].d
467 ; VBITS_GE_1024-NEXT: fadd d0, d0, [[RDX]]
478 ; VBITS_GE_2048-NEXT: faddv [[RDX:d[0-9]+]], [[PG]], [[OP]].d
479 ; VBITS_GE_2048-NEXT: fadd d0, d0, [[RDX]]