Lines Matching refs:RES

49 ; CHECK-NEXT: frintp [[RES:z[0-9]+]].h, [[PG]]/m, [[OP]].h
50 ; CHECK-NEXT: st1h { [[RES]].h }, [[PG]], [x0]
62 ; VBITS_GE_512-NEXT: frintp [[RES:z[0-9]+]].h, [[PG]]/m, [[OP]].h
63 ; VBITS_GE_512-NEXT: st1h { [[RES]].h }, [[PG]], [x0]
86 ; VBITS_GE_1024-NEXT: frintp [[RES:z[0-9]+]].h, [[PG]]/m, [[OP]].h
87 ; VBITS_GE_1024-NEXT: st1h { [[RES]].h }, [[PG]], [x0]
99 ; VBITS_GE_2048-NEXT: frintp [[RES:z[0-9]+]].h, [[PG]]/m, [[OP]].h
100 ; VBITS_GE_2048-NEXT: st1h { [[RES]].h }, [[PG]], [x0]
130 ; CHECK-NEXT: frintp [[RES:z[0-9]+]].s, [[PG]]/m, [[OP]].s
131 ; CHECK-NEXT: st1w { [[RES]].s }, [[PG]], [x0]
143 ; VBITS_GE_512-NEXT: frintp [[RES:z[0-9]+]].s, [[PG]]/m, [[OP]].s
144 ; VBITS_GE_512-NEXT: st1w { [[RES]].s }, [[PG]], [x0]
167 ; VBITS_GE_1024-NEXT: frintp [[RES:z[0-9]+]].s, [[PG]]/m, [[OP]].s
168 ; VBITS_GE_1024-NEXT: st1w { [[RES]].s }, [[PG]], [x0]
180 ; VBITS_GE_2048-NEXT: frintp [[RES:z[0-9]+]].s, [[PG]]/m, [[OP]].s
181 ; VBITS_GE_2048-NEXT: st1w { [[RES]].s }, [[PG]], [x0]
211 ; CHECK-NEXT: frintp [[RES:z[0-9]+]].d, [[PG]]/m, [[OP]].d
212 ; CHECK-NEXT: st1d { [[RES]].d }, [[PG]], [x0]
224 ; VBITS_GE_512-NEXT: frintp [[RES:z[0-9]+]].d, [[PG]]/m, [[OP]].d
225 ; VBITS_GE_512-NEXT: st1d { [[RES]].d }, [[PG]], [x0]
248 ; VBITS_GE_1024-NEXT: frintp [[RES:z[0-9]+]].d, [[PG]]/m, [[OP]].d
249 ; VBITS_GE_1024-NEXT: st1d { [[RES]].d }, [[PG]], [x0]
261 ; VBITS_GE_2048-NEXT: frintp [[RES:z[0-9]+]].d, [[PG]]/m, [[OP]].d
262 ; VBITS_GE_2048-NEXT: st1d { [[RES]].d }, [[PG]], [x0]
296 ; CHECK-NEXT: frintm [[RES:z[0-9]+]].h, [[PG]]/m, [[OP]].h
297 ; CHECK-NEXT: st1h { [[RES]].h }, [[PG]], [x0]
309 ; VBITS_GE_512-NEXT: frintm [[RES:z[0-9]+]].h, [[PG]]/m, [[OP]].h
310 ; VBITS_GE_512-NEXT: st1h { [[RES]].h }, [[PG]], [x0]
333 ; VBITS_GE_1024-NEXT: frintm [[RES:z[0-9]+]].h, [[PG]]/m, [[OP]].h
334 ; VBITS_GE_1024-NEXT: st1h { [[RES]].h }, [[PG]], [x0]
346 ; VBITS_GE_2048-NEXT: frintm [[RES:z[0-9]+]].h, [[PG]]/m, [[OP]].h
347 ; VBITS_GE_2048-NEXT: st1h { [[RES]].h }, [[PG]], [x0]
377 ; CHECK-NEXT: frintm [[RES:z[0-9]+]].s, [[PG]]/m, [[OP]].s
378 ; CHECK-NEXT: st1w { [[RES]].s }, [[PG]], [x0]
390 ; VBITS_GE_512-NEXT: frintm [[RES:z[0-9]+]].s, [[PG]]/m, [[OP]].s
391 ; VBITS_GE_512-NEXT: st1w { [[RES]].s }, [[PG]], [x0]
414 ; VBITS_GE_1024-NEXT: frintm [[RES:z[0-9]+]].s, [[PG]]/m, [[OP]].s
415 ; VBITS_GE_1024-NEXT: st1w { [[RES]].s }, [[PG]], [x0]
427 ; VBITS_GE_2048-NEXT: frintm [[RES:z[0-9]+]].s, [[PG]]/m, [[OP]].s
428 ; VBITS_GE_2048-NEXT: st1w { [[RES]].s }, [[PG]], [x0]
458 ; CHECK-NEXT: frintm [[RES:z[0-9]+]].d, [[PG]]/m, [[OP]].d
459 ; CHECK-NEXT: st1d { [[RES]].d }, [[PG]], [x0]
471 ; VBITS_GE_512-NEXT: frintm [[RES:z[0-9]+]].d, [[PG]]/m, [[OP]].d
472 ; VBITS_GE_512-NEXT: st1d { [[RES]].d }, [[PG]], [x0]
495 ; VBITS_GE_1024-NEXT: frintm [[RES:z[0-9]+]].d, [[PG]]/m, [[OP]].d
496 ; VBITS_GE_1024-NEXT: st1d { [[RES]].d }, [[PG]], [x0]
508 ; VBITS_GE_2048-NEXT: frintm [[RES:z[0-9]+]].d, [[PG]]/m, [[OP]].d
509 ; VBITS_GE_2048-NEXT: st1d { [[RES]].d }, [[PG]], [x0]
543 ; CHECK-NEXT: frinti [[RES:z[0-9]+]].h, [[PG]]/m, [[OP]].h
544 ; CHECK-NEXT: st1h { [[RES]].h }, [[PG]], [x0]
556 ; VBITS_GE_512-NEXT: frinti [[RES:z[0-9]+]].h, [[PG]]/m, [[OP]].h
557 ; VBITS_GE_512-NEXT: st1h { [[RES]].h }, [[PG]], [x0]
580 ; VBITS_GE_1024-NEXT: frinti [[RES:z[0-9]+]].h, [[PG]]/m, [[OP]].h
581 ; VBITS_GE_1024-NEXT: st1h { [[RES]].h }, [[PG]], [x0]
593 ; VBITS_GE_2048-NEXT: frinti [[RES:z[0-9]+]].h, [[PG]]/m, [[OP]].h
594 ; VBITS_GE_2048-NEXT: st1h { [[RES]].h }, [[PG]], [x0]
624 ; CHECK-NEXT: frinti [[RES:z[0-9]+]].s, [[PG]]/m, [[OP]].s
625 ; CHECK-NEXT: st1w { [[RES]].s }, [[PG]], [x0]
637 ; VBITS_GE_512-NEXT: frinti [[RES:z[0-9]+]].s, [[PG]]/m, [[OP]].s
638 ; VBITS_GE_512-NEXT: st1w { [[RES]].s }, [[PG]], [x0]
661 ; VBITS_GE_1024-NEXT: frinti [[RES:z[0-9]+]].s, [[PG]]/m, [[OP]].s
662 ; VBITS_GE_1024-NEXT: st1w { [[RES]].s }, [[PG]], [x0]
674 ; VBITS_GE_2048-NEXT: frinti [[RES:z[0-9]+]].s, [[PG]]/m, [[OP]].s
675 ; VBITS_GE_2048-NEXT: st1w { [[RES]].s }, [[PG]], [x0]
705 ; CHECK-NEXT: frinti [[RES:z[0-9]+]].d, [[PG]]/m, [[OP]].d
706 ; CHECK-NEXT: st1d { [[RES]].d }, [[PG]], [x0]
718 ; VBITS_GE_512-NEXT: frinti [[RES:z[0-9]+]].d, [[PG]]/m, [[OP]].d
719 ; VBITS_GE_512-NEXT: st1d { [[RES]].d }, [[PG]], [x0]
742 ; VBITS_GE_1024-NEXT: frinti [[RES:z[0-9]+]].d, [[PG]]/m, [[OP]].d
743 ; VBITS_GE_1024-NEXT: st1d { [[RES]].d }, [[PG]], [x0]
755 ; VBITS_GE_2048-NEXT: frinti [[RES:z[0-9]+]].d, [[PG]]/m, [[OP]].d
756 ; VBITS_GE_2048-NEXT: st1d { [[RES]].d }, [[PG]], [x0]
790 ; CHECK-NEXT: frintx [[RES:z[0-9]+]].h, [[PG]]/m, [[OP]].h
791 ; CHECK-NEXT: st1h { [[RES]].h }, [[PG]], [x0]
803 ; VBITS_GE_512-NEXT: frintx [[RES:z[0-9]+]].h, [[PG]]/m, [[OP]].h
804 ; VBITS_GE_512-NEXT: st1h { [[RES]].h }, [[PG]], [x0]
827 ; VBITS_GE_1024-NEXT: frintx [[RES:z[0-9]+]].h, [[PG]]/m, [[OP]].h
828 ; VBITS_GE_1024-NEXT: st1h { [[RES]].h }, [[PG]], [x0]
840 ; VBITS_GE_2048-NEXT: frintx [[RES:z[0-9]+]].h, [[PG]]/m, [[OP]].h
841 ; VBITS_GE_2048-NEXT: st1h { [[RES]].h }, [[PG]], [x0]
871 ; CHECK-NEXT: frintx [[RES:z[0-9]+]].s, [[PG]]/m, [[OP]].s
872 ; CHECK-NEXT: st1w { [[RES]].s }, [[PG]], [x0]
884 ; VBITS_GE_512-NEXT: frintx [[RES:z[0-9]+]].s, [[PG]]/m, [[OP]].s
885 ; VBITS_GE_512-NEXT: st1w { [[RES]].s }, [[PG]], [x0]
908 ; VBITS_GE_1024-NEXT: frintx [[RES:z[0-9]+]].s, [[PG]]/m, [[OP]].s
909 ; VBITS_GE_1024-NEXT: st1w { [[RES]].s }, [[PG]], [x0]
921 ; VBITS_GE_2048-NEXT: frintx [[RES:z[0-9]+]].s, [[PG]]/m, [[OP]].s
922 ; VBITS_GE_2048-NEXT: st1w { [[RES]].s }, [[PG]], [x0]
952 ; CHECK-NEXT: frintx [[RES:z[0-9]+]].d, [[PG]]/m, [[OP]].d
953 ; CHECK-NEXT: st1d { [[RES]].d }, [[PG]], [x0]
965 ; VBITS_GE_512-NEXT: frintx [[RES:z[0-9]+]].d, [[PG]]/m, [[OP]].d
966 ; VBITS_GE_512-NEXT: st1d { [[RES]].d }, [[PG]], [x0]
989 ; VBITS_GE_1024-NEXT: frintx [[RES:z[0-9]+]].d, [[PG]]/m, [[OP]].d
990 ; VBITS_GE_1024-NEXT: st1d { [[RES]].d }, [[PG]], [x0]
1002 ; VBITS_GE_2048-NEXT: frintx [[RES:z[0-9]+]].d, [[PG]]/m, [[OP]].d
1003 ; VBITS_GE_2048-NEXT: st1d { [[RES]].d }, [[PG]], [x0]
1037 ; CHECK-NEXT: frinta [[RES:z[0-9]+]].h, [[PG]]/m, [[OP]].h
1038 ; CHECK-NEXT: st1h { [[RES]].h }, [[PG]], [x0]
1050 ; VBITS_GE_512-NEXT: frinta [[RES:z[0-9]+]].h, [[PG]]/m, [[OP]].h
1051 ; VBITS_GE_512-NEXT: st1h { [[RES]].h }, [[PG]], [x0]
1074 ; VBITS_GE_1024-NEXT: frinta [[RES:z[0-9]+]].h, [[PG]]/m, [[OP]].h
1075 ; VBITS_GE_1024-NEXT: st1h { [[RES]].h }, [[PG]], [x0]
1087 ; VBITS_GE_2048-NEXT: frinta [[RES:z[0-9]+]].h, [[PG]]/m, [[OP]].h
1088 ; VBITS_GE_2048-NEXT: st1h { [[RES]].h }, [[PG]], [x0]
1118 ; CHECK-NEXT: frinta [[RES:z[0-9]+]].s, [[PG]]/m, [[OP]].s
1119 ; CHECK-NEXT: st1w { [[RES]].s }, [[PG]], [x0]
1131 ; VBITS_GE_512-NEXT: frinta [[RES:z[0-9]+]].s, [[PG]]/m, [[OP]].s
1132 ; VBITS_GE_512-NEXT: st1w { [[RES]].s }, [[PG]], [x0]
1155 ; VBITS_GE_1024-NEXT: frinta [[RES:z[0-9]+]].s, [[PG]]/m, [[OP]].s
1156 ; VBITS_GE_1024-NEXT: st1w { [[RES]].s }, [[PG]], [x0]
1168 ; VBITS_GE_2048-NEXT: frinta [[RES:z[0-9]+]].s, [[PG]]/m, [[OP]].s
1169 ; VBITS_GE_2048-NEXT: st1w { [[RES]].s }, [[PG]], [x0]
1199 ; CHECK-NEXT: frinta [[RES:z[0-9]+]].d, [[PG]]/m, [[OP]].d
1200 ; CHECK-NEXT: st1d { [[RES]].d }, [[PG]], [x0]
1212 ; VBITS_GE_512-NEXT: frinta [[RES:z[0-9]+]].d, [[PG]]/m, [[OP]].d
1213 ; VBITS_GE_512-NEXT: st1d { [[RES]].d }, [[PG]], [x0]
1236 ; VBITS_GE_1024-NEXT: frinta [[RES:z[0-9]+]].d, [[PG]]/m, [[OP]].d
1237 ; VBITS_GE_1024-NEXT: st1d { [[RES]].d }, [[PG]], [x0]
1249 ; VBITS_GE_2048-NEXT: frinta [[RES:z[0-9]+]].d, [[PG]]/m, [[OP]].d
1250 ; VBITS_GE_2048-NEXT: st1d { [[RES]].d }, [[PG]], [x0]
1284 ; CHECK-NEXT: frintz [[RES:z[0-9]+]].h, [[PG]]/m, [[OP]].h
1285 ; CHECK-NEXT: st1h { [[RES]].h }, [[PG]], [x0]
1297 ; VBITS_GE_512-NEXT: frintz [[RES:z[0-9]+]].h, [[PG]]/m, [[OP]].h
1298 ; VBITS_GE_512-NEXT: st1h { [[RES]].h }, [[PG]], [x0]
1321 ; VBITS_GE_1024-NEXT: frintz [[RES:z[0-9]+]].h, [[PG]]/m, [[OP]].h
1322 ; VBITS_GE_1024-NEXT: st1h { [[RES]].h }, [[PG]], [x0]
1334 ; VBITS_GE_2048-NEXT: frintz [[RES:z[0-9]+]].h, [[PG]]/m, [[OP]].h
1335 ; VBITS_GE_2048-NEXT: st1h { [[RES]].h }, [[PG]], [x0]
1365 ; CHECK-NEXT: frintz [[RES:z[0-9]+]].s, [[PG]]/m, [[OP]].s
1366 ; CHECK-NEXT: st1w { [[RES]].s }, [[PG]], [x0]
1378 ; VBITS_GE_512-NEXT: frintz [[RES:z[0-9]+]].s, [[PG]]/m, [[OP]].s
1379 ; VBITS_GE_512-NEXT: st1w { [[RES]].s }, [[PG]], [x0]
1402 ; VBITS_GE_1024-NEXT: frintz [[RES:z[0-9]+]].s, [[PG]]/m, [[OP]].s
1403 ; VBITS_GE_1024-NEXT: st1w { [[RES]].s }, [[PG]], [x0]
1415 ; VBITS_GE_2048-NEXT: frintz [[RES:z[0-9]+]].s, [[PG]]/m, [[OP]].s
1416 ; VBITS_GE_2048-NEXT: st1w { [[RES]].s }, [[PG]], [x0]
1446 ; CHECK-NEXT: frintz [[RES:z[0-9]+]].d, [[PG]]/m, [[OP]].d
1447 ; CHECK-NEXT: st1d { [[RES]].d }, [[PG]], [x0]
1459 ; VBITS_GE_512-NEXT: frintz [[RES:z[0-9]+]].d, [[PG]]/m, [[OP]].d
1460 ; VBITS_GE_512-NEXT: st1d { [[RES]].d }, [[PG]], [x0]
1483 ; VBITS_GE_1024-NEXT: frintz [[RES:z[0-9]+]].d, [[PG]]/m, [[OP]].d
1484 ; VBITS_GE_1024-NEXT: st1d { [[RES]].d }, [[PG]], [x0]
1496 ; VBITS_GE_2048-NEXT: frintz [[RES:z[0-9]+]].d, [[PG]]/m, [[OP]].d
1497 ; VBITS_GE_2048-NEXT: st1d { [[RES]].d }, [[PG]], [x0]