Lines Matching refs:st1d

212 ; CHECK-NEXT: st1d { [[RES]].d }, [[PG]], [x0]
225 ; VBITS_GE_512-NEXT: st1d { [[RES]].d }, [[PG]], [x0]
235 ; VBITS_EQ_256-DAG: st1d { [[RES_LO]].d }, [[PG]], [x0]
236 ; VBITS_EQ_256-DAG: st1d { [[RES_HI]].d }, [[PG]], [x[[A_HI]]
249 ; VBITS_GE_1024-NEXT: st1d { [[RES]].d }, [[PG]], [x0]
262 ; VBITS_GE_2048-NEXT: st1d { [[RES]].d }, [[PG]], [x0]
459 ; CHECK-NEXT: st1d { [[RES]].d }, [[PG]], [x0]
472 ; VBITS_GE_512-NEXT: st1d { [[RES]].d }, [[PG]], [x0]
482 ; VBITS_EQ_256-DAG: st1d { [[RES_LO]].d }, [[PG]], [x0]
483 ; VBITS_EQ_256-DAG: st1d { [[RES_HI]].d }, [[PG]], [x[[A_HI]]
496 ; VBITS_GE_1024-NEXT: st1d { [[RES]].d }, [[PG]], [x0]
509 ; VBITS_GE_2048-NEXT: st1d { [[RES]].d }, [[PG]], [x0]
706 ; CHECK-NEXT: st1d { [[RES]].d }, [[PG]], [x0]
719 ; VBITS_GE_512-NEXT: st1d { [[RES]].d }, [[PG]], [x0]
729 ; VBITS_EQ_256-DAG: st1d { [[RES_LO]].d }, [[PG]], [x0]
730 ; VBITS_EQ_256-DAG: st1d { [[RES_HI]].d }, [[PG]], [x[[A_HI]]
743 ; VBITS_GE_1024-NEXT: st1d { [[RES]].d }, [[PG]], [x0]
756 ; VBITS_GE_2048-NEXT: st1d { [[RES]].d }, [[PG]], [x0]
953 ; CHECK-NEXT: st1d { [[RES]].d }, [[PG]], [x0]
966 ; VBITS_GE_512-NEXT: st1d { [[RES]].d }, [[PG]], [x0]
976 ; VBITS_EQ_256-DAG: st1d { [[RES_LO]].d }, [[PG]], [x0]
977 ; VBITS_EQ_256-DAG: st1d { [[RES_HI]].d }, [[PG]], [x[[A_HI]]
990 ; VBITS_GE_1024-NEXT: st1d { [[RES]].d }, [[PG]], [x0]
1003 ; VBITS_GE_2048-NEXT: st1d { [[RES]].d }, [[PG]], [x0]
1200 ; CHECK-NEXT: st1d { [[RES]].d }, [[PG]], [x0]
1213 ; VBITS_GE_512-NEXT: st1d { [[RES]].d }, [[PG]], [x0]
1223 ; VBITS_EQ_256-DAG: st1d { [[RES_LO]].d }, [[PG]], [x0]
1224 ; VBITS_EQ_256-DAG: st1d { [[RES_HI]].d }, [[PG]], [x[[A_HI]]
1237 ; VBITS_GE_1024-NEXT: st1d { [[RES]].d }, [[PG]], [x0]
1250 ; VBITS_GE_2048-NEXT: st1d { [[RES]].d }, [[PG]], [x0]
1447 ; CHECK-NEXT: st1d { [[RES]].d }, [[PG]], [x0]
1460 ; VBITS_GE_512-NEXT: st1d { [[RES]].d }, [[PG]], [x0]
1470 ; VBITS_EQ_256-DAG: st1d { [[RES_LO]].d }, [[PG]], [x0]
1471 ; VBITS_EQ_256-DAG: st1d { [[RES_HI]].d }, [[PG]], [x[[A_HI]]
1484 ; VBITS_GE_1024-NEXT: st1d { [[RES]].d }, [[PG]], [x0]
1497 ; VBITS_GE_2048-NEXT: st1d { [[RES]].d }, [[PG]], [x0]