Lines Matching refs:umin
1148 ; CHECK: umin v0.8b, v0.8b, v1.8b
1150 %res = call <8 x i8> @llvm.umin.v8i8(<8 x i8> %op1, <8 x i8> %op2)
1157 ; CHECK: umin v0.16b, v0.16b, v1.16b
1159 %res = call <16 x i8> @llvm.umin.v16i8(<16 x i8> %op1, <16 x i8> %op2)
1168 ; CHECK-NEXT: umin [[RES:z[0-9]+]].b, [[PG]]/m, [[OP1]].b, [[OP2]].b
1173 %res = call <32 x i8> @llvm.umin.v32i8(<32 x i8> %op1, <32 x i8> %op2)
1183 ; VBITS_GE_512-NEXT: umin [[RES:z[0-9]+]].b, [[PG]]/m, [[OP1]].b, [[OP2]].b
1194 ; VBITS_EQ_256-DAG: umin [[RES_LO:z[0-9]+]].b, [[PG]]/m, [[OP1_LO]].b, [[OP2_LO]].b
1195 ; VBITS_EQ_256-DAG: umin [[RES_HI:z[0-9]+]].b, [[PG]]/m, [[OP1_HI]].b, [[OP2_HI]].b
1200 %res = call <64 x i8> @llvm.umin.v64i8(<64 x i8> %op1, <64 x i8> %op2)
1210 ; VBITS_GE_1024-NEXT: umin [[RES:z[0-9]+]].b, [[PG]]/m, [[OP1]].b, [[OP2]].b
1215 %res = call <128 x i8> @llvm.umin.v128i8(<128 x i8> %op1, <128 x i8> %op2)
1225 ; VBITS_GE_2048-NEXT: umin [[RES:z[0-9]+]].b, [[PG]]/m, [[OP1]].b, [[OP2]].b
1230 %res = call <256 x i8> @llvm.umin.v256i8(<256 x i8> %op1, <256 x i8> %op2)
1238 ; CHECK: umin v0.4h, v0.4h, v1.4h
1240 %res = call <4 x i16> @llvm.umin.v4i16(<4 x i16> %op1, <4 x i16> %op2)
1247 ; CHECK: umin v0.8h, v0.8h, v1.8h
1249 %res = call <8 x i16> @llvm.umin.v8i16(<8 x i16> %op1, <8 x i16> %op2)
1258 ; CHECK-NEXT: umin [[RES:z[0-9]+]].h, [[PG]]/m, [[OP1]].h, [[OP2]].h
1263 %res = call <16 x i16> @llvm.umin.v16i16(<16 x i16> %op1, <16 x i16> %op2)
1273 ; VBITS_GE_512-NEXT: umin [[RES:z[0-9]+]].h, [[PG]]/m, [[OP1]].h, [[OP2]].h
1285 ; VBITS_EQ_256-DAG: umin [[RES_LO:z[0-9]+]].h, [[PG]]/m, [[OP1_LO]].h, [[OP2_LO]].h
1286 ; VBITS_EQ_256-DAG: umin [[RES_HI:z[0-9]+]].h, [[PG]]/m, [[OP1_HI]].h, [[OP2_HI]].h
1292 %res = call <32 x i16> @llvm.umin.v32i16(<32 x i16> %op1, <32 x i16> %op2)
1302 ; VBITS_GE_1024-NEXT: umin [[RES:z[0-9]+]].h, [[PG]]/m, [[OP1]].h, [[OP2]].h
1307 %res = call <64 x i16> @llvm.umin.v64i16(<64 x i16> %op1, <64 x i16> %op2)
1317 ; VBITS_GE_2048-NEXT: umin [[RES:z[0-9]+]].h, [[PG]]/m, [[OP1]].h, [[OP2]].h
1322 %res = call <128 x i16> @llvm.umin.v128i16(<128 x i16> %op1, <128 x i16> %op2)
1330 ; CHECK: umin v0.2s, v0.2s, v1.2s
1332 %res = call <2 x i32> @llvm.umin.v2i32(<2 x i32> %op1, <2 x i32> %op2)
1339 ; CHECK: umin v0.4s, v0.4s, v1.4s
1341 %res = call <4 x i32> @llvm.umin.v4i32(<4 x i32> %op1, <4 x i32> %op2)
1350 ; CHECK-NEXT: umin [[RES:z[0-9]+]].s, [[PG]]/m, [[OP1]].s, [[OP2]].s
1355 %res = call <8 x i32> @llvm.umin.v8i32(<8 x i32> %op1, <8 x i32> %op2)
1365 ; VBITS_GE_512-NEXT: umin [[RES:z[0-9]+]].s, [[PG]]/m, [[OP1]].s, [[OP2]].s
1377 ; VBITS_EQ_256-DAG: umin [[RES_LO:z[0-9]+]].s, [[PG]]/m, [[OP1_LO]].s, [[OP2_LO]].s
1378 ; VBITS_EQ_256-DAG: umin [[RES_HI:z[0-9]+]].s, [[PG]]/m, [[OP1_HI]].s, [[OP2_HI]].s
1384 %res = call <16 x i32> @llvm.umin.v16i32(<16 x i32> %op1, <16 x i32> %op2)
1394 ; VBITS_GE_1024-NEXT: umin [[RES:z[0-9]+]].s, [[PG]]/m, [[OP1]].s, [[OP2]].s
1399 %res = call <32 x i32> @llvm.umin.v32i32(<32 x i32> %op1, <32 x i32> %op2)
1409 ; VBITS_GE_2048-NEXT: umin [[RES:z[0-9]+]].s, [[PG]]/m, [[OP1]].s, [[OP2]].s
1414 %res = call <64 x i32> @llvm.umin.v64i32(<64 x i32> %op1, <64 x i32> %op2)
1423 ; CHECK-NEXT: umin z0.d, [[PG]]/m, z0.d, z1.d
1425 %res = call <1 x i64> @llvm.umin.v1i64(<1 x i64> %op1, <1 x i64> %op2)
1433 ; CHECK-NEXT: umin z0.d, [[PG]]/m, z0.d, z1.d
1435 %res = call <2 x i64> @llvm.umin.v2i64(<2 x i64> %op1, <2 x i64> %op2)
1444 ; CHECK-NEXT: umin [[RES:z[0-9]+]].d, [[PG]]/m, [[OP1]].d, [[OP2]].d
1449 %res = call <4 x i64> @llvm.umin.v4i64(<4 x i64> %op1, <4 x i64> %op2)
1459 ; VBITS_GE_512-NEXT: umin [[RES:z[0-9]+]].d, [[PG]]/m, [[OP1]].d, [[OP2]].d
1471 ; VBITS_EQ_256-DAG: umin [[RES_LO:z[0-9]+]].d, [[PG]]/m, [[OP1_LO]].d, [[OP2_LO]].d
1472 ; VBITS_EQ_256-DAG: umin [[RES_HI:z[0-9]+]].d, [[PG]]/m, [[OP1_HI]].d, [[OP2_HI]].d
1478 %res = call <8 x i64> @llvm.umin.v8i64(<8 x i64> %op1, <8 x i64> %op2)
1488 ; VBITS_GE_1024-NEXT: umin [[RES:z[0-9]+]].d, [[PG]]/m, [[OP1]].d, [[OP2]].d
1493 %res = call <16 x i64> @llvm.umin.v16i64(<16 x i64> %op1, <16 x i64> %op2)
1503 ; VBITS_GE_2048-NEXT: umin [[RES:z[0-9]+]].d, [[PG]]/m, [[OP1]].d, [[OP2]].d
1508 %res = call <32 x i64> @llvm.umin.v32i64(<32 x i64> %op1, <32 x i64> %op2)
1565 declare <8 x i8> @llvm.umin.v8i8(<8 x i8>, <8 x i8>)
1566 declare <16 x i8> @llvm.umin.v16i8(<16 x i8>, <16 x i8>)
1567 declare <32 x i8> @llvm.umin.v32i8(<32 x i8>, <32 x i8>)
1568 declare <64 x i8> @llvm.umin.v64i8(<64 x i8>, <64 x i8>)
1569 declare <128 x i8> @llvm.umin.v128i8(<128 x i8>, <128 x i8>)
1570 declare <256 x i8> @llvm.umin.v256i8(<256 x i8>, <256 x i8>)
1571 declare <4 x i16> @llvm.umin.v4i16(<4 x i16>, <4 x i16>)
1572 declare <8 x i16> @llvm.umin.v8i16(<8 x i16>, <8 x i16>)
1573 declare <16 x i16> @llvm.umin.v16i16(<16 x i16>, <16 x i16>)
1574 declare <32 x i16> @llvm.umin.v32i16(<32 x i16>, <32 x i16>)
1575 declare <64 x i16> @llvm.umin.v64i16(<64 x i16>, <64 x i16>)
1576 declare <128 x i16> @llvm.umin.v128i16(<128 x i16>, <128 x i16>)
1577 declare <2 x i32> @llvm.umin.v2i32(<2 x i32>, <2 x i32>)
1578 declare <4 x i32> @llvm.umin.v4i32(<4 x i32>, <4 x i32>)
1579 declare <8 x i32> @llvm.umin.v8i32(<8 x i32>, <8 x i32>)
1580 declare <16 x i32> @llvm.umin.v16i32(<16 x i32>, <16 x i32>)
1581 declare <32 x i32> @llvm.umin.v32i32(<32 x i32>, <32 x i32>)
1582 declare <64 x i32> @llvm.umin.v64i32(<64 x i32>, <64 x i32>)
1583 declare <1 x i64> @llvm.umin.v1i64(<1 x i64>, <1 x i64>)
1584 declare <2 x i64> @llvm.umin.v2i64(<2 x i64>, <2 x i64>)
1585 declare <4 x i64> @llvm.umin.v4i64(<4 x i64>, <4 x i64>)
1586 declare <8 x i64> @llvm.umin.v8i64(<8 x i64>, <8 x i64>)
1587 declare <16 x i64> @llvm.umin.v16i64(<16 x i64>, <16 x i64>)
1588 declare <32 x i64> @llvm.umin.v32i64(<32 x i64>, <32 x i64>)