Lines Matching refs:cmplt
529 ; CHECK: cmplt p0.b, p0/z, z0.b, #4
539 ; CHECK: cmplt p0.b, p0/z, z0.b, #4
551 ; CHECK: cmplt p0.b, p0/z, z0.b, #4
555 %out = call <vscale x 16 x i1> @llvm.aarch64.sve.cmplt.wide.nxv16i8(<vscale x 16 x i1> %pg,
563 ; CHECK: cmplt p0.h, p0/z, z0.h, #-16
573 ; CHECK: cmplt p0.h, p0/z, z0.h, #-16
585 ; CHECK: cmplt p0.h, p0/z, z0.h, #-16
589 %out = call <vscale x 8 x i1> @llvm.aarch64.sve.cmplt.wide.nxv8i16(<vscale x 8 x i1> %pg,
597 ; CHECK: cmplt p0.s, p0/z, z0.s, #15
607 ; CHECK: cmplt p0.s, p0/z, z0.s, #15
619 ; CHECK: cmplt p0.s, p0/z, z0.s, #15
623 %out = call <vscale x 4 x i1> @llvm.aarch64.sve.cmplt.wide.nxv4i32(<vscale x 4 x i1> %pg,
631 ; CHECK: cmplt p0.d, p0/z, z0.d, #0
641 ; CHECK: cmplt p0.d, p0/z, z0.d, #0
1347 declare <vscale x 16 x i1> @llvm.aarch64.sve.cmplt.wide.nxv16i8(<vscale x 16 x i1>, <vscale x 16 x …
1348 declare <vscale x 8 x i1> @llvm.aarch64.sve.cmplt.wide.nxv8i16(<vscale x 8 x i1>, <vscale x 8 x i16…
1349 declare <vscale x 4 x i1> @llvm.aarch64.sve.cmplt.wide.nxv4i32(<vscale x 4 x i1>, <vscale x 4 x i32…