Lines Matching refs:fadd
4 ; Same as vecreduce-fadd-legalization.ll, but without fmf.
6 declare half @llvm.vector.reduce.fadd.f16.v1f16(half, <1 x half>)
7 declare float @llvm.vector.reduce.fadd.f32.v1f32(float, <1 x float>)
8 declare double @llvm.vector.reduce.fadd.f64.v1f64(double, <1 x double>)
9 declare fp128 @llvm.vector.reduce.fadd.f128.v1f128(fp128, <1 x fp128>)
11 declare float @llvm.vector.reduce.fadd.f32.v3f32(float, <3 x float>)
12 declare float @llvm.vector.reduce.fadd.f32.v5f32(float, <5 x float>)
13 declare fp128 @llvm.vector.reduce.fadd.f128.v2f128(fp128, <2 x fp128>)
14 declare float @llvm.vector.reduce.fadd.f32.v16f32(float, <16 x float>)
21 ; CHECK-NEXT: fadd s0, s1, s0
24 %b = call half @llvm.vector.reduce.fadd.f16.v1f16(half %s, <1 x half> %a)
32 %b = call half @llvm.vector.reduce.fadd.f16.v1f16(half -0.0, <1 x half> %a)
40 ; CHECK-NEXT: fadd s0, s1, s0
42 %b = call float @llvm.vector.reduce.fadd.f32.v1f32(float %s, <1 x float> %a)
52 %b = call float @llvm.vector.reduce.fadd.f32.v1f32(float -0.0, <1 x float> %a)
59 ; CHECK-NEXT: fadd d0, d1, d0
61 %b = call double @llvm.vector.reduce.fadd.f64.v1f64(double %s, <1 x double> %a)
69 %b = call double @llvm.vector.reduce.fadd.f64.v1f64(double -0.0, <1 x double> %a)
83 %b = call fp128 @llvm.vector.reduce.fadd.f128.v1f128(fp128 %s, <1 x fp128> %a)
91 …%b = call fp128 @llvm.vector.reduce.fadd.f128.v1f128(fp128 0xL00000000000000008000000000000000, <1…
98 ; CHECK-NEXT: fadd s1, s1, s0
100 ; CHECK-NEXT: fadd s1, s1, s2
102 ; CHECK-NEXT: fadd s0, s1, s0
104 %b = call float @llvm.vector.reduce.fadd.f32.v3f32(float %s, <3 x float> %a)
113 ; CHECK-NEXT: fadd s0, s0, s1
115 %b = call float @llvm.vector.reduce.fadd.f32.v3f32(float -0.0, <3 x float> %a)
122 ; CHECK-NEXT: fadd s0, s5, s0
123 ; CHECK-NEXT: fadd s0, s0, s1
124 ; CHECK-NEXT: fadd s0, s0, s2
125 ; CHECK-NEXT: fadd s0, s0, s3
126 ; CHECK-NEXT: fadd s0, s0, s4
128 %b = call float @llvm.vector.reduce.fadd.f32.v5f32(float %s, <5 x float> %a)
135 ; CHECK-NEXT: fadd s0, s0, s1
136 ; CHECK-NEXT: fadd s0, s0, s2
137 ; CHECK-NEXT: fadd s0, s0, s3
138 ; CHECK-NEXT: fadd s0, s0, s4
140 %b = call float @llvm.vector.reduce.fadd.f32.v5f32(float -0.0, <5 x float> %a)
158 %b = call fp128 @llvm.vector.reduce.fadd.f128.v2f128(fp128 %s, <2 x fp128> %a)
169 …%b = call fp128 @llvm.vector.reduce.fadd.f128.v2f128(fp128 0xL00000000000000008000000000000000, <2…
179 ; CHECK-NEXT: fadd s0, s4, s0
180 ; CHECK-NEXT: fadd s0, s0, s24
181 ; CHECK-NEXT: fadd s0, s0, s23
182 ; CHECK-NEXT: fadd s0, s0, s22
184 ; CHECK-NEXT: fadd s0, s0, s1
186 ; CHECK-NEXT: fadd s0, s0, s21
188 ; CHECK-NEXT: fadd s0, s0, s20
189 ; CHECK-NEXT: fadd s0, s0, s19
191 ; CHECK-NEXT: fadd s0, s0, s2
193 ; CHECK-NEXT: fadd s0, s0, s18
195 ; CHECK-NEXT: fadd s0, s0, s17
196 ; CHECK-NEXT: fadd s0, s0, s16
198 ; CHECK-NEXT: fadd s0, s0, s3
200 ; CHECK-NEXT: fadd s0, s0, s7
202 ; CHECK-NEXT: fadd s0, s0, s6
203 ; CHECK-NEXT: fadd s0, s0, s5
205 %b = call float @llvm.vector.reduce.fadd.f32.v16f32(float %s, <16 x float> %a)
215 ; CHECK-NEXT: fadd s0, s0, s22
216 ; CHECK-NEXT: fadd s0, s0, s21
218 ; CHECK-NEXT: fadd s0, s0, s1
220 ; CHECK-NEXT: fadd s0, s0, s20
222 ; CHECK-NEXT: fadd s0, s0, s19
223 ; CHECK-NEXT: fadd s0, s0, s18
225 ; CHECK-NEXT: fadd s0, s0, s2
227 ; CHECK-NEXT: fadd s0, s0, s17
229 ; CHECK-NEXT: fadd s0, s0, s16
230 ; CHECK-NEXT: fadd s0, s0, s7
232 ; CHECK-NEXT: fadd s0, s0, s3
234 ; CHECK-NEXT: fadd s0, s0, s6
236 ; CHECK-NEXT: fadd s0, s0, s5
237 ; CHECK-NEXT: fadd s0, s0, s4
239 %b = call float @llvm.vector.reduce.fadd.f32.v16f32(float -0.0, <16 x float> %a)