Lines Matching refs:VI
3 ; RUN: opt -S -mtriple=amdgcn-- -mcpu=tonga -amdgpu-codegenprepare %s | FileCheck -check-prefix=VI …
11 ; VI-LABEL: @add_i3(
12 ; VI-NEXT: [[TMP1:%.*]] = zext i3 [[A:%.*]] to i32
13 ; VI-NEXT: [[TMP2:%.*]] = zext i3 [[B:%.*]] to i32
14 ; VI-NEXT: [[TMP3:%.*]] = add nuw nsw i32 [[TMP1]], [[TMP2]]
15 ; VI-NEXT: [[TMP4:%.*]] = trunc i32 [[TMP3]] to i3
16 ; VI-NEXT: store volatile i3 [[TMP4]], i3 addrspace(1)* undef
17 ; VI-NEXT: ret void
30 ; VI-LABEL: @add_nsw_i3(
31 ; VI-NEXT: [[TMP1:%.*]] = zext i3 [[A:%.*]] to i32
32 ; VI-NEXT: [[TMP2:%.*]] = zext i3 [[B:%.*]] to i32
33 ; VI-NEXT: [[TMP3:%.*]] = add nuw nsw i32 [[TMP1]], [[TMP2]]
34 ; VI-NEXT: [[TMP4:%.*]] = trunc i32 [[TMP3]] to i3
35 ; VI-NEXT: store volatile i3 [[TMP4]], i3 addrspace(1)* undef
36 ; VI-NEXT: ret void
49 ; VI-LABEL: @add_nuw_i3(
50 ; VI-NEXT: [[TMP1:%.*]] = zext i3 [[A:%.*]] to i32
51 ; VI-NEXT: [[TMP2:%.*]] = zext i3 [[B:%.*]] to i32
52 ; VI-NEXT: [[TMP3:%.*]] = add nuw nsw i32 [[TMP1]], [[TMP2]]
53 ; VI-NEXT: [[TMP4:%.*]] = trunc i32 [[TMP3]] to i3
54 ; VI-NEXT: store volatile i3 [[TMP4]], i3 addrspace(1)* undef
55 ; VI-NEXT: ret void
68 ; VI-LABEL: @add_nuw_nsw_i3(
69 ; VI-NEXT: [[TMP1:%.*]] = zext i3 [[A:%.*]] to i32
70 ; VI-NEXT: [[TMP2:%.*]] = zext i3 [[B:%.*]] to i32
71 ; VI-NEXT: [[TMP3:%.*]] = add nuw nsw i32 [[TMP1]], [[TMP2]]
72 ; VI-NEXT: [[TMP4:%.*]] = trunc i32 [[TMP3]] to i3
73 ; VI-NEXT: store volatile i3 [[TMP4]], i3 addrspace(1)* undef
74 ; VI-NEXT: ret void
87 ; VI-LABEL: @sub_i3(
88 ; VI-NEXT: [[TMP1:%.*]] = zext i3 [[A:%.*]] to i32
89 ; VI-NEXT: [[TMP2:%.*]] = zext i3 [[B:%.*]] to i32
90 ; VI-NEXT: [[TMP3:%.*]] = sub nsw i32 [[TMP1]], [[TMP2]]
91 ; VI-NEXT: [[TMP4:%.*]] = trunc i32 [[TMP3]] to i3
92 ; VI-NEXT: store volatile i3 [[TMP4]], i3 addrspace(1)* undef
93 ; VI-NEXT: ret void
106 ; VI-LABEL: @sub_nsw_i3(
107 ; VI-NEXT: [[TMP1:%.*]] = zext i3 [[A:%.*]] to i32
108 ; VI-NEXT: [[TMP2:%.*]] = zext i3 [[B:%.*]] to i32
109 ; VI-NEXT: [[TMP3:%.*]] = sub nsw i32 [[TMP1]], [[TMP2]]
110 ; VI-NEXT: [[TMP4:%.*]] = trunc i32 [[TMP3]] to i3
111 ; VI-NEXT: store volatile i3 [[TMP4]], i3 addrspace(1)* undef
112 ; VI-NEXT: ret void
125 ; VI-LABEL: @sub_nuw_i3(
126 ; VI-NEXT: [[TMP1:%.*]] = zext i3 [[A:%.*]] to i32
127 ; VI-NEXT: [[TMP2:%.*]] = zext i3 [[B:%.*]] to i32
128 ; VI-NEXT: [[TMP3:%.*]] = sub nuw nsw i32 [[TMP1]], [[TMP2]]
129 ; VI-NEXT: [[TMP4:%.*]] = trunc i32 [[TMP3]] to i3
130 ; VI-NEXT: store volatile i3 [[TMP4]], i3 addrspace(1)* undef
131 ; VI-NEXT: ret void
144 ; VI-LABEL: @sub_nuw_nsw_i3(
145 ; VI-NEXT: [[TMP1:%.*]] = zext i3 [[A:%.*]] to i32
146 ; VI-NEXT: [[TMP2:%.*]] = zext i3 [[B:%.*]] to i32
147 ; VI-NEXT: [[TMP3:%.*]] = sub nuw nsw i32 [[TMP1]], [[TMP2]]
148 ; VI-NEXT: [[TMP4:%.*]] = trunc i32 [[TMP3]] to i3
149 ; VI-NEXT: store volatile i3 [[TMP4]], i3 addrspace(1)* undef
150 ; VI-NEXT: ret void
163 ; VI-LABEL: @mul_i3(
164 ; VI-NEXT: [[TMP1:%.*]] = zext i3 [[A:%.*]] to i32
165 ; VI-NEXT: [[TMP2:%.*]] = zext i3 [[B:%.*]] to i32
166 ; VI-NEXT: [[TMP3:%.*]] = mul nuw i32 [[TMP1]], [[TMP2]]
167 ; VI-NEXT: [[TMP4:%.*]] = trunc i32 [[TMP3]] to i3
168 ; VI-NEXT: store volatile i3 [[TMP4]], i3 addrspace(1)* undef
169 ; VI-NEXT: ret void
182 ; VI-LABEL: @mul_nsw_i3(
183 ; VI-NEXT: [[TMP1:%.*]] = zext i3 [[A:%.*]] to i32
184 ; VI-NEXT: [[TMP2:%.*]] = zext i3 [[B:%.*]] to i32
185 ; VI-NEXT: [[TMP3:%.*]] = mul nuw i32 [[TMP1]], [[TMP2]]
186 ; VI-NEXT: [[TMP4:%.*]] = trunc i32 [[TMP3]] to i3
187 ; VI-NEXT: store volatile i3 [[TMP4]], i3 addrspace(1)* undef
188 ; VI-NEXT: ret void
201 ; VI-LABEL: @mul_nuw_i3(
202 ; VI-NEXT: [[TMP1:%.*]] = zext i3 [[A:%.*]] to i32
203 ; VI-NEXT: [[TMP2:%.*]] = zext i3 [[B:%.*]] to i32
204 ; VI-NEXT: [[TMP3:%.*]] = mul nuw nsw i32 [[TMP1]], [[TMP2]]
205 ; VI-NEXT: [[TMP4:%.*]] = trunc i32 [[TMP3]] to i3
206 ; VI-NEXT: store volatile i3 [[TMP4]], i3 addrspace(1)* undef
207 ; VI-NEXT: ret void
220 ; VI-LABEL: @mul_nuw_nsw_i3(
221 ; VI-NEXT: [[TMP1:%.*]] = zext i3 [[A:%.*]] to i32
222 ; VI-NEXT: [[TMP2:%.*]] = zext i3 [[B:%.*]] to i32
223 ; VI-NEXT: [[TMP3:%.*]] = mul nuw nsw i32 [[TMP1]], [[TMP2]]
224 ; VI-NEXT: [[TMP4:%.*]] = trunc i32 [[TMP3]] to i3
225 ; VI-NEXT: store volatile i3 [[TMP4]], i3 addrspace(1)* undef
226 ; VI-NEXT: ret void
239 ; VI-LABEL: @shl_i3(
240 ; VI-NEXT: [[TMP1:%.*]] = zext i3 [[A:%.*]] to i32
241 ; VI-NEXT: [[TMP2:%.*]] = zext i3 [[B:%.*]] to i32
242 ; VI-NEXT: [[TMP3:%.*]] = shl nuw nsw i32 [[TMP1]], [[TMP2]]
243 ; VI-NEXT: [[TMP4:%.*]] = trunc i32 [[TMP3]] to i3
244 ; VI-NEXT: store volatile i3 [[TMP4]], i3 addrspace(1)* undef
245 ; VI-NEXT: ret void
258 ; VI-LABEL: @shl_nsw_i3(
259 ; VI-NEXT: [[TMP1:%.*]] = zext i3 [[A:%.*]] to i32
260 ; VI-NEXT: [[TMP2:%.*]] = zext i3 [[B:%.*]] to i32
261 ; VI-NEXT: [[TMP3:%.*]] = shl nuw nsw i32 [[TMP1]], [[TMP2]]
262 ; VI-NEXT: [[TMP4:%.*]] = trunc i32 [[TMP3]] to i3
263 ; VI-NEXT: store volatile i3 [[TMP4]], i3 addrspace(1)* undef
264 ; VI-NEXT: ret void
277 ; VI-LABEL: @shl_nuw_i3(
278 ; VI-NEXT: [[TMP1:%.*]] = zext i3 [[A:%.*]] to i32
279 ; VI-NEXT: [[TMP2:%.*]] = zext i3 [[B:%.*]] to i32
280 ; VI-NEXT: [[TMP3:%.*]] = shl nuw nsw i32 [[TMP1]], [[TMP2]]
281 ; VI-NEXT: [[TMP4:%.*]] = trunc i32 [[TMP3]] to i3
282 ; VI-NEXT: store volatile i3 [[TMP4]], i3 addrspace(1)* undef
283 ; VI-NEXT: ret void
296 ; VI-LABEL: @shl_nuw_nsw_i3(
297 ; VI-NEXT: [[TMP1:%.*]] = zext i3 [[A:%.*]] to i32
298 ; VI-NEXT: [[TMP2:%.*]] = zext i3 [[B:%.*]] to i32
299 ; VI-NEXT: [[TMP3:%.*]] = shl nuw nsw i32 [[TMP1]], [[TMP2]]
300 ; VI-NEXT: [[TMP4:%.*]] = trunc i32 [[TMP3]] to i3
301 ; VI-NEXT: store volatile i3 [[TMP4]], i3 addrspace(1)* undef
302 ; VI-NEXT: ret void
315 ; VI-LABEL: @lshr_i3(
316 ; VI-NEXT: [[TMP1:%.*]] = zext i3 [[A:%.*]] to i32
317 ; VI-NEXT: [[TMP2:%.*]] = zext i3 [[B:%.*]] to i32
318 ; VI-NEXT: [[TMP3:%.*]] = lshr i32 [[TMP1]], [[TMP2]]
319 ; VI-NEXT: [[TMP4:%.*]] = trunc i32 [[TMP3]] to i3
320 ; VI-NEXT: store volatile i3 [[TMP4]], i3 addrspace(1)* undef
321 ; VI-NEXT: ret void
334 ; VI-LABEL: @lshr_exact_i3(
335 ; VI-NEXT: [[TMP1:%.*]] = zext i3 [[A:%.*]] to i32
336 ; VI-NEXT: [[TMP2:%.*]] = zext i3 [[B:%.*]] to i32
337 ; VI-NEXT: [[TMP3:%.*]] = lshr exact i32 [[TMP1]], [[TMP2]]
338 ; VI-NEXT: [[TMP4:%.*]] = trunc i32 [[TMP3]] to i3
339 ; VI-NEXT: store volatile i3 [[TMP4]], i3 addrspace(1)* undef
340 ; VI-NEXT: ret void
353 ; VI-LABEL: @ashr_i3(
354 ; VI-NEXT: [[TMP1:%.*]] = sext i3 [[A:%.*]] to i32
355 ; VI-NEXT: [[TMP2:%.*]] = sext i3 [[B:%.*]] to i32
356 ; VI-NEXT: [[TMP3:%.*]] = ashr i32 [[TMP1]], [[TMP2]]
357 ; VI-NEXT: [[TMP4:%.*]] = trunc i32 [[TMP3]] to i3
358 ; VI-NEXT: store volatile i3 [[TMP4]], i3 addrspace(1)* undef
359 ; VI-NEXT: ret void
372 ; VI-LABEL: @ashr_exact_i3(
373 ; VI-NEXT: [[TMP1:%.*]] = sext i3 [[A:%.*]] to i32
374 ; VI-NEXT: [[TMP2:%.*]] = sext i3 [[B:%.*]] to i32
375 ; VI-NEXT: [[TMP3:%.*]] = ashr exact i32 [[TMP1]], [[TMP2]]
376 ; VI-NEXT: [[TMP4:%.*]] = trunc i32 [[TMP3]] to i3
377 ; VI-NEXT: store volatile i3 [[TMP4]], i3 addrspace(1)* undef
378 ; VI-NEXT: ret void
391 ; VI-LABEL: @and_i3(
392 ; VI-NEXT: [[TMP1:%.*]] = zext i3 [[A:%.*]] to i32
393 ; VI-NEXT: [[TMP2:%.*]] = zext i3 [[B:%.*]] to i32
394 ; VI-NEXT: [[TMP3:%.*]] = and i32 [[TMP1]], [[TMP2]]
395 ; VI-NEXT: [[TMP4:%.*]] = trunc i32 [[TMP3]] to i3
396 ; VI-NEXT: store volatile i3 [[TMP4]], i3 addrspace(1)* undef
397 ; VI-NEXT: ret void
410 ; VI-LABEL: @or_i3(
411 ; VI-NEXT: [[TMP1:%.*]] = zext i3 [[A:%.*]] to i32
412 ; VI-NEXT: [[TMP2:%.*]] = zext i3 [[B:%.*]] to i32
413 ; VI-NEXT: [[TMP3:%.*]] = or i32 [[TMP1]], [[TMP2]]
414 ; VI-NEXT: [[TMP4:%.*]] = trunc i32 [[TMP3]] to i3
415 ; VI-NEXT: store volatile i3 [[TMP4]], i3 addrspace(1)* undef
416 ; VI-NEXT: ret void
429 ; VI-LABEL: @xor_i3(
430 ; VI-NEXT: [[TMP1:%.*]] = zext i3 [[A:%.*]] to i32
431 ; VI-NEXT: [[TMP2:%.*]] = zext i3 [[B:%.*]] to i32
432 ; VI-NEXT: [[TMP3:%.*]] = xor i32 [[TMP1]], [[TMP2]]
433 ; VI-NEXT: [[TMP4:%.*]] = trunc i32 [[TMP3]] to i3
434 ; VI-NEXT: store volatile i3 [[TMP4]], i3 addrspace(1)* undef
435 ; VI-NEXT: ret void
449 ; VI-LABEL: @select_eq_i3(
450 ; VI-NEXT: [[TMP1:%.*]] = zext i3 [[A:%.*]] to i32
451 ; VI-NEXT: [[TMP2:%.*]] = zext i3 [[B:%.*]] to i32
452 ; VI-NEXT: [[TMP3:%.*]] = icmp eq i32 [[TMP1]], [[TMP2]]
453 ; VI-NEXT: [[TMP4:%.*]] = zext i3 [[A]] to i32
454 ; VI-NEXT: [[TMP5:%.*]] = zext i3 [[B]] to i32
455 ; VI-NEXT: [[TMP6:%.*]] = select i1 [[TMP3]], i32 [[TMP4]], i32 [[TMP5]]
456 ; VI-NEXT: [[TMP7:%.*]] = trunc i32 [[TMP6]] to i3
457 ; VI-NEXT: store volatile i3 [[TMP7]], i3 addrspace(1)* undef
458 ; VI-NEXT: ret void
473 ; VI-LABEL: @select_ne_i3(
474 ; VI-NEXT: [[TMP1:%.*]] = zext i3 [[A:%.*]] to i32
475 ; VI-NEXT: [[TMP2:%.*]] = zext i3 [[B:%.*]] to i32
476 ; VI-NEXT: [[TMP3:%.*]] = icmp ne i32 [[TMP1]], [[TMP2]]
477 ; VI-NEXT: [[TMP4:%.*]] = zext i3 [[A]] to i32
478 ; VI-NEXT: [[TMP5:%.*]] = zext i3 [[B]] to i32
479 ; VI-NEXT: [[TMP6:%.*]] = select i1 [[TMP3]], i32 [[TMP4]], i32 [[TMP5]]
480 ; VI-NEXT: [[TMP7:%.*]] = trunc i32 [[TMP6]] to i3
481 ; VI-NEXT: store volatile i3 [[TMP7]], i3 addrspace(1)* undef
482 ; VI-NEXT: ret void
497 ; VI-LABEL: @select_ugt_i3(
498 ; VI-NEXT: [[TMP1:%.*]] = zext i3 [[A:%.*]] to i32
499 ; VI-NEXT: [[TMP2:%.*]] = zext i3 [[B:%.*]] to i32
500 ; VI-NEXT: [[TMP3:%.*]] = icmp ugt i32 [[TMP1]], [[TMP2]]
501 ; VI-NEXT: [[TMP4:%.*]] = zext i3 [[A]] to i32
502 ; VI-NEXT: [[TMP5:%.*]] = zext i3 [[B]] to i32
503 ; VI-NEXT: [[TMP6:%.*]] = select i1 [[TMP3]], i32 [[TMP4]], i32 [[TMP5]]
504 ; VI-NEXT: [[TMP7:%.*]] = trunc i32 [[TMP6]] to i3
505 ; VI-NEXT: store volatile i3 [[TMP7]], i3 addrspace(1)* undef
506 ; VI-NEXT: ret void
521 ; VI-LABEL: @select_uge_i3(
522 ; VI-NEXT: [[TMP1:%.*]] = zext i3 [[A:%.*]] to i32
523 ; VI-NEXT: [[TMP2:%.*]] = zext i3 [[B:%.*]] to i32
524 ; VI-NEXT: [[TMP3:%.*]] = icmp uge i32 [[TMP1]], [[TMP2]]
525 ; VI-NEXT: [[TMP4:%.*]] = zext i3 [[A]] to i32
526 ; VI-NEXT: [[TMP5:%.*]] = zext i3 [[B]] to i32
527 ; VI-NEXT: [[TMP6:%.*]] = select i1 [[TMP3]], i32 [[TMP4]], i32 [[TMP5]]
528 ; VI-NEXT: [[TMP7:%.*]] = trunc i32 [[TMP6]] to i3
529 ; VI-NEXT: store volatile i3 [[TMP7]], i3 addrspace(1)* undef
530 ; VI-NEXT: ret void
545 ; VI-LABEL: @select_ult_i3(
546 ; VI-NEXT: [[TMP1:%.*]] = zext i3 [[A:%.*]] to i32
547 ; VI-NEXT: [[TMP2:%.*]] = zext i3 [[B:%.*]] to i32
548 ; VI-NEXT: [[TMP3:%.*]] = icmp ult i32 [[TMP1]], [[TMP2]]
549 ; VI-NEXT: [[TMP4:%.*]] = zext i3 [[A]] to i32
550 ; VI-NEXT: [[TMP5:%.*]] = zext i3 [[B]] to i32
551 ; VI-NEXT: [[TMP6:%.*]] = select i1 [[TMP3]], i32 [[TMP4]], i32 [[TMP5]]
552 ; VI-NEXT: [[TMP7:%.*]] = trunc i32 [[TMP6]] to i3
553 ; VI-NEXT: store volatile i3 [[TMP7]], i3 addrspace(1)* undef
554 ; VI-NEXT: ret void
569 ; VI-LABEL: @select_ule_i3(
570 ; VI-NEXT: [[TMP1:%.*]] = zext i3 [[A:%.*]] to i32
571 ; VI-NEXT: [[TMP2:%.*]] = zext i3 [[B:%.*]] to i32
572 ; VI-NEXT: [[TMP3:%.*]] = icmp ule i32 [[TMP1]], [[TMP2]]
573 ; VI-NEXT: [[TMP4:%.*]] = zext i3 [[A]] to i32
574 ; VI-NEXT: [[TMP5:%.*]] = zext i3 [[B]] to i32
575 ; VI-NEXT: [[TMP6:%.*]] = select i1 [[TMP3]], i32 [[TMP4]], i32 [[TMP5]]
576 ; VI-NEXT: [[TMP7:%.*]] = trunc i32 [[TMP6]] to i3
577 ; VI-NEXT: store volatile i3 [[TMP7]], i3 addrspace(1)* undef
578 ; VI-NEXT: ret void
593 ; VI-LABEL: @select_sgt_i3(
594 ; VI-NEXT: [[TMP1:%.*]] = sext i3 [[A:%.*]] to i32
595 ; VI-NEXT: [[TMP2:%.*]] = sext i3 [[B:%.*]] to i32
596 ; VI-NEXT: [[TMP3:%.*]] = icmp sgt i32 [[TMP1]], [[TMP2]]
597 ; VI-NEXT: [[TMP4:%.*]] = sext i3 [[A]] to i32
598 ; VI-NEXT: [[TMP5:%.*]] = sext i3 [[B]] to i32
599 ; VI-NEXT: [[TMP6:%.*]] = select i1 [[TMP3]], i32 [[TMP4]], i32 [[TMP5]]
600 ; VI-NEXT: [[TMP7:%.*]] = trunc i32 [[TMP6]] to i3
601 ; VI-NEXT: store volatile i3 [[TMP7]], i3 addrspace(1)* undef
602 ; VI-NEXT: ret void
617 ; VI-LABEL: @select_sge_i3(
618 ; VI-NEXT: [[TMP1:%.*]] = sext i3 [[A:%.*]] to i32
619 ; VI-NEXT: [[TMP2:%.*]] = sext i3 [[B:%.*]] to i32
620 ; VI-NEXT: [[TMP3:%.*]] = icmp sge i32 [[TMP1]], [[TMP2]]
621 ; VI-NEXT: [[TMP4:%.*]] = sext i3 [[A]] to i32
622 ; VI-NEXT: [[TMP5:%.*]] = sext i3 [[B]] to i32
623 ; VI-NEXT: [[TMP6:%.*]] = select i1 [[TMP3]], i32 [[TMP4]], i32 [[TMP5]]
624 ; VI-NEXT: [[TMP7:%.*]] = trunc i32 [[TMP6]] to i3
625 ; VI-NEXT: store volatile i3 [[TMP7]], i3 addrspace(1)* undef
626 ; VI-NEXT: ret void
641 ; VI-LABEL: @select_slt_i3(
642 ; VI-NEXT: [[TMP1:%.*]] = sext i3 [[A:%.*]] to i32
643 ; VI-NEXT: [[TMP2:%.*]] = sext i3 [[B:%.*]] to i32
644 ; VI-NEXT: [[TMP3:%.*]] = icmp slt i32 [[TMP1]], [[TMP2]]
645 ; VI-NEXT: [[TMP4:%.*]] = sext i3 [[A]] to i32
646 ; VI-NEXT: [[TMP5:%.*]] = sext i3 [[B]] to i32
647 ; VI-NEXT: [[TMP6:%.*]] = select i1 [[TMP3]], i32 [[TMP4]], i32 [[TMP5]]
648 ; VI-NEXT: [[TMP7:%.*]] = trunc i32 [[TMP6]] to i3
649 ; VI-NEXT: store volatile i3 [[TMP7]], i3 addrspace(1)* undef
650 ; VI-NEXT: ret void
665 ; VI-LABEL: @select_sle_i3(
666 ; VI-NEXT: [[TMP1:%.*]] = sext i3 [[A:%.*]] to i32
667 ; VI-NEXT: [[TMP2:%.*]] = sext i3 [[B:%.*]] to i32
668 ; VI-NEXT: [[TMP3:%.*]] = icmp sle i32 [[TMP1]], [[TMP2]]
669 ; VI-NEXT: [[TMP4:%.*]] = sext i3 [[A]] to i32
670 ; VI-NEXT: [[TMP5:%.*]] = sext i3 [[B]] to i32
671 ; VI-NEXT: [[TMP6:%.*]] = select i1 [[TMP3]], i32 [[TMP4]], i32 [[TMP5]]
672 ; VI-NEXT: [[TMP7:%.*]] = trunc i32 [[TMP6]] to i3
673 ; VI-NEXT: store volatile i3 [[TMP7]], i3 addrspace(1)* undef
674 ; VI-NEXT: ret void
689 ; VI-LABEL: @bitreverse_i3(
690 ; VI-NEXT: [[TMP1:%.*]] = zext i3 [[A:%.*]] to i32
691 ; VI-NEXT: [[TMP2:%.*]] = call i32 @llvm.bitreverse.i32(i32 [[TMP1]])
692 ; VI-NEXT: [[TMP3:%.*]] = lshr i32 [[TMP2]], 29
693 ; VI-NEXT: [[TMP4:%.*]] = trunc i32 [[TMP3]] to i3
694 ; VI-NEXT: store volatile i3 [[TMP4]], i3 addrspace(1)* undef
695 ; VI-NEXT: ret void
708 ; VI-LABEL: @add_i16(
709 ; VI-NEXT: [[TMP1:%.*]] = zext i16 [[A:%.*]] to i32
710 ; VI-NEXT: [[TMP2:%.*]] = zext i16 [[B:%.*]] to i32
711 ; VI-NEXT: [[TMP3:%.*]] = add nuw nsw i32 [[TMP1]], [[TMP2]]
712 ; VI-NEXT: [[TMP4:%.*]] = trunc i32 [[TMP3]] to i16
713 ; VI-NEXT: store volatile i16 [[TMP4]], i16 addrspace(1)* undef
714 ; VI-NEXT: ret void
727 ; VI-LABEL: @constant_add_i16(
728 ; VI-NEXT: store volatile i16 3, i16 addrspace(1)* undef
729 ; VI-NEXT: ret void
742 ; VI-LABEL: @constant_add_nsw_i16(
743 ; VI-NEXT: store volatile i16 3, i16 addrspace(1)* undef
744 ; VI-NEXT: ret void
757 ; VI-LABEL: @constant_add_nuw_i16(
758 ; VI-NEXT: store volatile i16 3, i16 addrspace(1)* undef
759 ; VI-NEXT: ret void
772 ; VI-LABEL: @add_nsw_i16(
773 ; VI-NEXT: [[TMP1:%.*]] = zext i16 [[A:%.*]] to i32
774 ; VI-NEXT: [[TMP2:%.*]] = zext i16 [[B:%.*]] to i32
775 ; VI-NEXT: [[TMP3:%.*]] = add nuw nsw i32 [[TMP1]], [[TMP2]]
776 ; VI-NEXT: [[TMP4:%.*]] = trunc i32 [[TMP3]] to i16
777 ; VI-NEXT: store volatile i16 [[TMP4]], i16 addrspace(1)* undef
778 ; VI-NEXT: ret void
791 ; VI-LABEL: @add_nuw_i16(
792 ; VI-NEXT: [[TMP1:%.*]] = zext i16 [[A:%.*]] to i32
793 ; VI-NEXT: [[TMP2:%.*]] = zext i16 [[B:%.*]] to i32
794 ; VI-NEXT: [[TMP3:%.*]] = add nuw nsw i32 [[TMP1]], [[TMP2]]
795 ; VI-NEXT: [[TMP4:%.*]] = trunc i32 [[TMP3]] to i16
796 ; VI-NEXT: store volatile i16 [[TMP4]], i16 addrspace(1)* undef
797 ; VI-NEXT: ret void
810 ; VI-LABEL: @add_nuw_nsw_i16(
811 ; VI-NEXT: [[TMP1:%.*]] = zext i16 [[A:%.*]] to i32
812 ; VI-NEXT: [[TMP2:%.*]] = zext i16 [[B:%.*]] to i32
813 ; VI-NEXT: [[TMP3:%.*]] = add nuw nsw i32 [[TMP1]], [[TMP2]]
814 ; VI-NEXT: [[TMP4:%.*]] = trunc i32 [[TMP3]] to i16
815 ; VI-NEXT: store volatile i16 [[TMP4]], i16 addrspace(1)* undef
816 ; VI-NEXT: ret void
829 ; VI-LABEL: @sub_i16(
830 ; VI-NEXT: [[TMP1:%.*]] = zext i16 [[A:%.*]] to i32
831 ; VI-NEXT: [[TMP2:%.*]] = zext i16 [[B:%.*]] to i32
832 ; VI-NEXT: [[TMP3:%.*]] = sub nsw i32 [[TMP1]], [[TMP2]]
833 ; VI-NEXT: [[TMP4:%.*]] = trunc i32 [[TMP3]] to i16
834 ; VI-NEXT: store volatile i16 [[TMP4]], i16 addrspace(1)* undef
835 ; VI-NEXT: ret void
848 ; VI-LABEL: @sub_nsw_i16(
849 ; VI-NEXT: [[TMP1:%.*]] = zext i16 [[A:%.*]] to i32
850 ; VI-NEXT: [[TMP2:%.*]] = zext i16 [[B:%.*]] to i32
851 ; VI-NEXT: [[TMP3:%.*]] = sub nsw i32 [[TMP1]], [[TMP2]]
852 ; VI-NEXT: [[TMP4:%.*]] = trunc i32 [[TMP3]] to i16
853 ; VI-NEXT: store volatile i16 [[TMP4]], i16 addrspace(1)* undef
854 ; VI-NEXT: ret void
867 ; VI-LABEL: @sub_nuw_i16(
868 ; VI-NEXT: [[TMP1:%.*]] = zext i16 [[A:%.*]] to i32
869 ; VI-NEXT: [[TMP2:%.*]] = zext i16 [[B:%.*]] to i32
870 ; VI-NEXT: [[TMP3:%.*]] = sub nuw nsw i32 [[TMP1]], [[TMP2]]
871 ; VI-NEXT: [[TMP4:%.*]] = trunc i32 [[TMP3]] to i16
872 ; VI-NEXT: store volatile i16 [[TMP4]], i16 addrspace(1)* undef
873 ; VI-NEXT: ret void
886 ; VI-LABEL: @sub_nuw_nsw_i16(
887 ; VI-NEXT: [[TMP1:%.*]] = zext i16 [[A:%.*]] to i32
888 ; VI-NEXT: [[TMP2:%.*]] = zext i16 [[B:%.*]] to i32
889 ; VI-NEXT: [[TMP3:%.*]] = sub nuw nsw i32 [[TMP1]], [[TMP2]]
890 ; VI-NEXT: [[TMP4:%.*]] = trunc i32 [[TMP3]] to i16
891 ; VI-NEXT: store volatile i16 [[TMP4]], i16 addrspace(1)* undef
892 ; VI-NEXT: ret void
905 ; VI-LABEL: @mul_i16(
906 ; VI-NEXT: [[TMP1:%.*]] = zext i16 [[A:%.*]] to i32
907 ; VI-NEXT: [[TMP2:%.*]] = zext i16 [[B:%.*]] to i32
908 ; VI-NEXT: [[TMP3:%.*]] = mul nuw i32 [[TMP1]], [[TMP2]]
909 ; VI-NEXT: [[TMP4:%.*]] = trunc i32 [[TMP3]] to i16
910 ; VI-NEXT: store volatile i16 [[TMP4]], i16 addrspace(1)* undef
911 ; VI-NEXT: ret void
924 ; VI-LABEL: @mul_nsw_i16(
925 ; VI-NEXT: [[TMP1:%.*]] = zext i16 [[A:%.*]] to i32
926 ; VI-NEXT: [[TMP2:%.*]] = zext i16 [[B:%.*]] to i32
927 ; VI-NEXT: [[TMP3:%.*]] = mul nuw i32 [[TMP1]], [[TMP2]]
928 ; VI-NEXT: [[TMP4:%.*]] = trunc i32 [[TMP3]] to i16
929 ; VI-NEXT: store volatile i16 [[TMP4]], i16 addrspace(1)* undef
930 ; VI-NEXT: ret void
943 ; VI-LABEL: @mul_nuw_i16(
944 ; VI-NEXT: [[TMP1:%.*]] = zext i16 [[A:%.*]] to i32
945 ; VI-NEXT: [[TMP2:%.*]] = zext i16 [[B:%.*]] to i32
946 ; VI-NEXT: [[TMP3:%.*]] = mul nuw nsw i32 [[TMP1]], [[TMP2]]
947 ; VI-NEXT: [[TMP4:%.*]] = trunc i32 [[TMP3]] to i16
948 ; VI-NEXT: store volatile i16 [[TMP4]], i16 addrspace(1)* undef
949 ; VI-NEXT: ret void
962 ; VI-LABEL: @mul_nuw_nsw_i16(
963 ; VI-NEXT: [[TMP1:%.*]] = zext i16 [[A:%.*]] to i32
964 ; VI-NEXT: [[TMP2:%.*]] = zext i16 [[B:%.*]] to i32
965 ; VI-NEXT: [[TMP3:%.*]] = mul nuw nsw i32 [[TMP1]], [[TMP2]]
966 ; VI-NEXT: [[TMP4:%.*]] = trunc i32 [[TMP3]] to i16
967 ; VI-NEXT: store volatile i16 [[TMP4]], i16 addrspace(1)* undef
968 ; VI-NEXT: ret void
981 ; VI-LABEL: @shl_i16(
982 ; VI-NEXT: [[TMP1:%.*]] = zext i16 [[A:%.*]] to i32
983 ; VI-NEXT: [[TMP2:%.*]] = zext i16 [[B:%.*]] to i32
984 ; VI-NEXT: [[TMP3:%.*]] = shl nuw nsw i32 [[TMP1]], [[TMP2]]
985 ; VI-NEXT: [[TMP4:%.*]] = trunc i32 [[TMP3]] to i16
986 ; VI-NEXT: store volatile i16 [[TMP4]], i16 addrspace(1)* undef
987 ; VI-NEXT: ret void
1000 ; VI-LABEL: @shl_nsw_i16(
1001 ; VI-NEXT: [[TMP1:%.*]] = zext i16 [[A:%.*]] to i32
1002 ; VI-NEXT: [[TMP2:%.*]] = zext i16 [[B:%.*]] to i32
1003 ; VI-NEXT: [[TMP3:%.*]] = shl nuw nsw i32 [[TMP1]], [[TMP2]]
1004 ; VI-NEXT: [[TMP4:%.*]] = trunc i32 [[TMP3]] to i16
1005 ; VI-NEXT: store volatile i16 [[TMP4]], i16 addrspace(1)* undef
1006 ; VI-NEXT: ret void
1019 ; VI-LABEL: @shl_nuw_i16(
1020 ; VI-NEXT: [[TMP1:%.*]] = zext i16 [[A:%.*]] to i32
1021 ; VI-NEXT: [[TMP2:%.*]] = zext i16 [[B:%.*]] to i32
1022 ; VI-NEXT: [[TMP3:%.*]] = shl nuw nsw i32 [[TMP1]], [[TMP2]]
1023 ; VI-NEXT: [[TMP4:%.*]] = trunc i32 [[TMP3]] to i16
1024 ; VI-NEXT: store volatile i16 [[TMP4]], i16 addrspace(1)* undef
1025 ; VI-NEXT: ret void
1038 ; VI-LABEL: @shl_nuw_nsw_i16(
1039 ; VI-NEXT: [[TMP1:%.*]] = zext i16 [[A:%.*]] to i32
1040 ; VI-NEXT: [[TMP2:%.*]] = zext i16 [[B:%.*]] to i32
1041 ; VI-NEXT: [[TMP3:%.*]] = shl nuw nsw i32 [[TMP1]], [[TMP2]]
1042 ; VI-NEXT: [[TMP4:%.*]] = trunc i32 [[TMP3]] to i16
1043 ; VI-NEXT: store volatile i16 [[TMP4]], i16 addrspace(1)* undef
1044 ; VI-NEXT: ret void
1057 ; VI-LABEL: @lshr_i16(
1058 ; VI-NEXT: [[TMP1:%.*]] = zext i16 [[A:%.*]] to i32
1059 ; VI-NEXT: [[TMP2:%.*]] = zext i16 [[B:%.*]] to i32
1060 ; VI-NEXT: [[TMP3:%.*]] = lshr i32 [[TMP1]], [[TMP2]]
1061 ; VI-NEXT: [[TMP4:%.*]] = trunc i32 [[TMP3]] to i16
1062 ; VI-NEXT: store volatile i16 [[TMP4]], i16 addrspace(1)* undef
1063 ; VI-NEXT: ret void
1076 ; VI-LABEL: @lshr_exact_i16(
1077 ; VI-NEXT: [[TMP1:%.*]] = zext i16 [[A:%.*]] to i32
1078 ; VI-NEXT: [[TMP2:%.*]] = zext i16 [[B:%.*]] to i32
1079 ; VI-NEXT: [[TMP3:%.*]] = lshr exact i32 [[TMP1]], [[TMP2]]
1080 ; VI-NEXT: [[TMP4:%.*]] = trunc i32 [[TMP3]] to i16
1081 ; VI-NEXT: store volatile i16 [[TMP4]], i16 addrspace(1)* undef
1082 ; VI-NEXT: ret void
1095 ; VI-LABEL: @ashr_i16(
1096 ; VI-NEXT: [[TMP1:%.*]] = sext i16 [[A:%.*]] to i32
1097 ; VI-NEXT: [[TMP2:%.*]] = sext i16 [[B:%.*]] to i32
1098 ; VI-NEXT: [[TMP3:%.*]] = ashr i32 [[TMP1]], [[TMP2]]
1099 ; VI-NEXT: [[TMP4:%.*]] = trunc i32 [[TMP3]] to i16
1100 ; VI-NEXT: store volatile i16 [[TMP4]], i16 addrspace(1)* undef
1101 ; VI-NEXT: ret void
1114 ; VI-LABEL: @ashr_exact_i16(
1115 ; VI-NEXT: [[TMP1:%.*]] = sext i16 [[A:%.*]] to i32
1116 ; VI-NEXT: [[TMP2:%.*]] = sext i16 [[B:%.*]] to i32
1117 ; VI-NEXT: [[TMP3:%.*]] = ashr exact i32 [[TMP1]], [[TMP2]]
1118 ; VI-NEXT: [[TMP4:%.*]] = trunc i32 [[TMP3]] to i16
1119 ; VI-NEXT: store volatile i16 [[TMP4]], i16 addrspace(1)* undef
1120 ; VI-NEXT: ret void
1133 ; VI-LABEL: @constant_lshr_exact_i16(
1134 ; VI-NEXT: store volatile i16 2, i16 addrspace(1)* undef
1135 ; VI-NEXT: ret void
1148 ; VI-LABEL: @and_i16(
1149 ; VI-NEXT: [[TMP1:%.*]] = zext i16 [[A:%.*]] to i32
1150 ; VI-NEXT: [[TMP2:%.*]] = zext i16 [[B:%.*]] to i32
1151 ; VI-NEXT: [[TMP3:%.*]] = and i32 [[TMP1]], [[TMP2]]
1152 ; VI-NEXT: [[TMP4:%.*]] = trunc i32 [[TMP3]] to i16
1153 ; VI-NEXT: store volatile i16 [[TMP4]], i16 addrspace(1)* undef
1154 ; VI-NEXT: ret void
1167 ; VI-LABEL: @or_i16(
1168 ; VI-NEXT: [[TMP1:%.*]] = zext i16 [[A:%.*]] to i32
1169 ; VI-NEXT: [[TMP2:%.*]] = zext i16 [[B:%.*]] to i32
1170 ; VI-NEXT: [[TMP3:%.*]] = or i32 [[TMP1]], [[TMP2]]
1171 ; VI-NEXT: [[TMP4:%.*]] = trunc i32 [[TMP3]] to i16
1172 ; VI-NEXT: store volatile i16 [[TMP4]], i16 addrspace(1)* undef
1173 ; VI-NEXT: ret void
1186 ; VI-LABEL: @xor_i16(
1187 ; VI-NEXT: [[TMP1:%.*]] = zext i16 [[A:%.*]] to i32
1188 ; VI-NEXT: [[TMP2:%.*]] = zext i16 [[B:%.*]] to i32
1189 ; VI-NEXT: [[TMP3:%.*]] = xor i32 [[TMP1]], [[TMP2]]
1190 ; VI-NEXT: [[TMP4:%.*]] = trunc i32 [[TMP3]] to i16
1191 ; VI-NEXT: store volatile i16 [[TMP4]], i16 addrspace(1)* undef
1192 ; VI-NEXT: ret void
1206 ; VI-LABEL: @select_eq_i16(
1207 ; VI-NEXT: [[TMP1:%.*]] = zext i16 [[A:%.*]] to i32
1208 ; VI-NEXT: [[TMP2:%.*]] = zext i16 [[B:%.*]] to i32
1209 ; VI-NEXT: [[TMP3:%.*]] = icmp eq i32 [[TMP1]], [[TMP2]]
1210 ; VI-NEXT: [[TMP4:%.*]] = zext i16 [[A]] to i32
1211 ; VI-NEXT: [[TMP5:%.*]] = zext i16 [[B]] to i32
1212 ; VI-NEXT: [[TMP6:%.*]] = select i1 [[TMP3]], i32 [[TMP4]], i32 [[TMP5]]
1213 ; VI-NEXT: [[TMP7:%.*]] = trunc i32 [[TMP6]] to i16
1214 ; VI-NEXT: store volatile i16 [[TMP7]], i16 addrspace(1)* undef
1215 ; VI-NEXT: ret void
1230 ; VI-LABEL: @select_ne_i16(
1231 ; VI-NEXT: [[TMP1:%.*]] = zext i16 [[A:%.*]] to i32
1232 ; VI-NEXT: [[TMP2:%.*]] = zext i16 [[B:%.*]] to i32
1233 ; VI-NEXT: [[TMP3:%.*]] = icmp ne i32 [[TMP1]], [[TMP2]]
1234 ; VI-NEXT: [[TMP4:%.*]] = zext i16 [[A]] to i32
1235 ; VI-NEXT: [[TMP5:%.*]] = zext i16 [[B]] to i32
1236 ; VI-NEXT: [[TMP6:%.*]] = select i1 [[TMP3]], i32 [[TMP4]], i32 [[TMP5]]
1237 ; VI-NEXT: [[TMP7:%.*]] = trunc i32 [[TMP6]] to i16
1238 ; VI-NEXT: store volatile i16 [[TMP7]], i16 addrspace(1)* undef
1239 ; VI-NEXT: ret void
1254 ; VI-LABEL: @select_ugt_i16(
1255 ; VI-NEXT: [[TMP1:%.*]] = zext i16 [[A:%.*]] to i32
1256 ; VI-NEXT: [[TMP2:%.*]] = zext i16 [[B:%.*]] to i32
1257 ; VI-NEXT: [[TMP3:%.*]] = icmp ugt i32 [[TMP1]], [[TMP2]]
1258 ; VI-NEXT: [[TMP4:%.*]] = zext i16 [[A]] to i32
1259 ; VI-NEXT: [[TMP5:%.*]] = zext i16 [[B]] to i32
1260 ; VI-NEXT: [[TMP6:%.*]] = select i1 [[TMP3]], i32 [[TMP4]], i32 [[TMP5]]
1261 ; VI-NEXT: [[TMP7:%.*]] = trunc i32 [[TMP6]] to i16
1262 ; VI-NEXT: store volatile i16 [[TMP7]], i16 addrspace(1)* undef
1263 ; VI-NEXT: ret void
1278 ; VI-LABEL: @select_uge_i16(
1279 ; VI-NEXT: [[TMP1:%.*]] = zext i16 [[A:%.*]] to i32
1280 ; VI-NEXT: [[TMP2:%.*]] = zext i16 [[B:%.*]] to i32
1281 ; VI-NEXT: [[TMP3:%.*]] = icmp uge i32 [[TMP1]], [[TMP2]]
1282 ; VI-NEXT: [[TMP4:%.*]] = zext i16 [[A]] to i32
1283 ; VI-NEXT: [[TMP5:%.*]] = zext i16 [[B]] to i32
1284 ; VI-NEXT: [[TMP6:%.*]] = select i1 [[TMP3]], i32 [[TMP4]], i32 [[TMP5]]
1285 ; VI-NEXT: [[TMP7:%.*]] = trunc i32 [[TMP6]] to i16
1286 ; VI-NEXT: store volatile i16 [[TMP7]], i16 addrspace(1)* undef
1287 ; VI-NEXT: ret void
1302 ; VI-LABEL: @select_ult_i16(
1303 ; VI-NEXT: [[TMP1:%.*]] = zext i16 [[A:%.*]] to i32
1304 ; VI-NEXT: [[TMP2:%.*]] = zext i16 [[B:%.*]] to i32
1305 ; VI-NEXT: [[TMP3:%.*]] = icmp ult i32 [[TMP1]], [[TMP2]]
1306 ; VI-NEXT: [[TMP4:%.*]] = zext i16 [[A]] to i32
1307 ; VI-NEXT: [[TMP5:%.*]] = zext i16 [[B]] to i32
1308 ; VI-NEXT: [[TMP6:%.*]] = select i1 [[TMP3]], i32 [[TMP4]], i32 [[TMP5]]
1309 ; VI-NEXT: [[TMP7:%.*]] = trunc i32 [[TMP6]] to i16
1310 ; VI-NEXT: store volatile i16 [[TMP7]], i16 addrspace(1)* undef
1311 ; VI-NEXT: ret void
1326 ; VI-LABEL: @select_ule_i16(
1327 ; VI-NEXT: [[TMP1:%.*]] = zext i16 [[A:%.*]] to i32
1328 ; VI-NEXT: [[TMP2:%.*]] = zext i16 [[B:%.*]] to i32
1329 ; VI-NEXT: [[TMP3:%.*]] = icmp ule i32 [[TMP1]], [[TMP2]]
1330 ; VI-NEXT: [[TMP4:%.*]] = zext i16 [[A]] to i32
1331 ; VI-NEXT: [[TMP5:%.*]] = zext i16 [[B]] to i32
1332 ; VI-NEXT: [[TMP6:%.*]] = select i1 [[TMP3]], i32 [[TMP4]], i32 [[TMP5]]
1333 ; VI-NEXT: [[TMP7:%.*]] = trunc i32 [[TMP6]] to i16
1334 ; VI-NEXT: store volatile i16 [[TMP7]], i16 addrspace(1)* undef
1335 ; VI-NEXT: ret void
1350 ; VI-LABEL: @select_sgt_i16(
1351 ; VI-NEXT: [[TMP1:%.*]] = sext i16 [[A:%.*]] to i32
1352 ; VI-NEXT: [[TMP2:%.*]] = sext i16 [[B:%.*]] to i32
1353 ; VI-NEXT: [[TMP3:%.*]] = icmp sgt i32 [[TMP1]], [[TMP2]]
1354 ; VI-NEXT: [[TMP4:%.*]] = sext i16 [[A]] to i32
1355 ; VI-NEXT: [[TMP5:%.*]] = sext i16 [[B]] to i32
1356 ; VI-NEXT: [[TMP6:%.*]] = select i1 [[TMP3]], i32 [[TMP4]], i32 [[TMP5]]
1357 ; VI-NEXT: [[TMP7:%.*]] = trunc i32 [[TMP6]] to i16
1358 ; VI-NEXT: store volatile i16 [[TMP7]], i16 addrspace(1)* undef
1359 ; VI-NEXT: ret void
1374 ; VI-LABEL: @select_sge_i16(
1375 ; VI-NEXT: [[TMP1:%.*]] = sext i16 [[A:%.*]] to i32
1376 ; VI-NEXT: [[TMP2:%.*]] = sext i16 [[B:%.*]] to i32
1377 ; VI-NEXT: [[TMP3:%.*]] = icmp sge i32 [[TMP1]], [[TMP2]]
1378 ; VI-NEXT: [[TMP4:%.*]] = sext i16 [[A]] to i32
1379 ; VI-NEXT: [[TMP5:%.*]] = sext i16 [[B]] to i32
1380 ; VI-NEXT: [[TMP6:%.*]] = select i1 [[TMP3]], i32 [[TMP4]], i32 [[TMP5]]
1381 ; VI-NEXT: [[TMP7:%.*]] = trunc i32 [[TMP6]] to i16
1382 ; VI-NEXT: store volatile i16 [[TMP7]], i16 addrspace(1)* undef
1383 ; VI-NEXT: ret void
1398 ; VI-LABEL: @select_slt_i16(
1399 ; VI-NEXT: [[TMP1:%.*]] = sext i16 [[A:%.*]] to i32
1400 ; VI-NEXT: [[TMP2:%.*]] = sext i16 [[B:%.*]] to i32
1401 ; VI-NEXT: [[TMP3:%.*]] = icmp slt i32 [[TMP1]], [[TMP2]]
1402 ; VI-NEXT: [[TMP4:%.*]] = sext i16 [[A]] to i32
1403 ; VI-NEXT: [[TMP5:%.*]] = sext i16 [[B]] to i32
1404 ; VI-NEXT: [[TMP6:%.*]] = select i1 [[TMP3]], i32 [[TMP4]], i32 [[TMP5]]
1405 ; VI-NEXT: [[TMP7:%.*]] = trunc i32 [[TMP6]] to i16
1406 ; VI-NEXT: store volatile i16 [[TMP7]], i16 addrspace(1)* undef
1407 ; VI-NEXT: ret void
1422 ; VI-LABEL: @select_sle_i16(
1423 ; VI-NEXT: [[TMP1:%.*]] = sext i16 [[A:%.*]] to i32
1424 ; VI-NEXT: [[TMP2:%.*]] = sext i16 [[B:%.*]] to i32
1425 ; VI-NEXT: [[TMP3:%.*]] = icmp sle i32 [[TMP1]], [[TMP2]]
1426 ; VI-NEXT: [[TMP4:%.*]] = sext i16 [[A]] to i32
1427 ; VI-NEXT: [[TMP5:%.*]] = sext i16 [[B]] to i32
1428 ; VI-NEXT: [[TMP6:%.*]] = select i1 [[TMP3]], i32 [[TMP4]], i32 [[TMP5]]
1429 ; VI-NEXT: [[TMP7:%.*]] = trunc i32 [[TMP6]] to i16
1430 ; VI-NEXT: store volatile i16 [[TMP7]], i16 addrspace(1)* undef
1431 ; VI-NEXT: ret void
1447 ; VI-LABEL: @bitreverse_i16(
1448 ; VI-NEXT: [[TMP1:%.*]] = zext i16 [[A:%.*]] to i32
1449 ; VI-NEXT: [[TMP2:%.*]] = call i32 @llvm.bitreverse.i32(i32 [[TMP1]])
1450 ; VI-NEXT: [[TMP3:%.*]] = lshr i32 [[TMP2]], 16
1451 ; VI-NEXT: [[TMP4:%.*]] = trunc i32 [[TMP3]] to i16
1452 ; VI-NEXT: store volatile i16 [[TMP4]], i16 addrspace(1)* undef
1453 ; VI-NEXT: ret void
1466 ; VI-LABEL: @add_3xi15(
1467 ; VI-NEXT: [[TMP1:%.*]] = zext <3 x i15> [[A:%.*]] to <3 x i32>
1468 ; VI-NEXT: [[TMP2:%.*]] = zext <3 x i15> [[B:%.*]] to <3 x i32>
1469 ; VI-NEXT: [[TMP3:%.*]] = add nuw nsw <3 x i32> [[TMP1]], [[TMP2]]
1470 ; VI-NEXT: [[TMP4:%.*]] = trunc <3 x i32> [[TMP3]] to <3 x i15>
1471 ; VI-NEXT: store volatile <3 x i15> [[TMP4]], <3 x i15> addrspace(1)* undef
1472 ; VI-NEXT: ret void
1485 ; VI-LABEL: @add_nsw_3xi15(
1486 ; VI-NEXT: [[TMP1:%.*]] = zext <3 x i15> [[A:%.*]] to <3 x i32>
1487 ; VI-NEXT: [[TMP2:%.*]] = zext <3 x i15> [[B:%.*]] to <3 x i32>
1488 ; VI-NEXT: [[TMP3:%.*]] = add nuw nsw <3 x i32> [[TMP1]], [[TMP2]]
1489 ; VI-NEXT: [[TMP4:%.*]] = trunc <3 x i32> [[TMP3]] to <3 x i15>
1490 ; VI-NEXT: store volatile <3 x i15> [[TMP4]], <3 x i15> addrspace(1)* undef
1491 ; VI-NEXT: ret void
1504 ; VI-LABEL: @add_nuw_3xi15(
1505 ; VI-NEXT: [[TMP1:%.*]] = zext <3 x i15> [[A:%.*]] to <3 x i32>
1506 ; VI-NEXT: [[TMP2:%.*]] = zext <3 x i15> [[B:%.*]] to <3 x i32>
1507 ; VI-NEXT: [[TMP3:%.*]] = add nuw nsw <3 x i32> [[TMP1]], [[TMP2]]
1508 ; VI-NEXT: [[TMP4:%.*]] = trunc <3 x i32> [[TMP3]] to <3 x i15>
1509 ; VI-NEXT: store volatile <3 x i15> [[TMP4]], <3 x i15> addrspace(1)* undef
1510 ; VI-NEXT: ret void
1523 ; VI-LABEL: @add_nuw_nsw_3xi15(
1524 ; VI-NEXT: [[TMP1:%.*]] = zext <3 x i15> [[A:%.*]] to <3 x i32>
1525 ; VI-NEXT: [[TMP2:%.*]] = zext <3 x i15> [[B:%.*]] to <3 x i32>
1526 ; VI-NEXT: [[TMP3:%.*]] = add nuw nsw <3 x i32> [[TMP1]], [[TMP2]]
1527 ; VI-NEXT: [[TMP4:%.*]] = trunc <3 x i32> [[TMP3]] to <3 x i15>
1528 ; VI-NEXT: store volatile <3 x i15> [[TMP4]], <3 x i15> addrspace(1)* undef
1529 ; VI-NEXT: ret void
1542 ; VI-LABEL: @sub_3xi15(
1543 ; VI-NEXT: [[TMP1:%.*]] = zext <3 x i15> [[A:%.*]] to <3 x i32>
1544 ; VI-NEXT: [[TMP2:%.*]] = zext <3 x i15> [[B:%.*]] to <3 x i32>
1545 ; VI-NEXT: [[TMP3:%.*]] = sub nsw <3 x i32> [[TMP1]], [[TMP2]]
1546 ; VI-NEXT: [[TMP4:%.*]] = trunc <3 x i32> [[TMP3]] to <3 x i15>
1547 ; VI-NEXT: store volatile <3 x i15> [[TMP4]], <3 x i15> addrspace(1)* undef
1548 ; VI-NEXT: ret void
1561 ; VI-LABEL: @sub_nsw_3xi15(
1562 ; VI-NEXT: [[TMP1:%.*]] = zext <3 x i15> [[A:%.*]] to <3 x i32>
1563 ; VI-NEXT: [[TMP2:%.*]] = zext <3 x i15> [[B:%.*]] to <3 x i32>
1564 ; VI-NEXT: [[TMP3:%.*]] = sub nsw <3 x i32> [[TMP1]], [[TMP2]]
1565 ; VI-NEXT: [[TMP4:%.*]] = trunc <3 x i32> [[TMP3]] to <3 x i15>
1566 ; VI-NEXT: store volatile <3 x i15> [[TMP4]], <3 x i15> addrspace(1)* undef
1567 ; VI-NEXT: ret void
1580 ; VI-LABEL: @sub_nuw_3xi15(
1581 ; VI-NEXT: [[TMP1:%.*]] = zext <3 x i15> [[A:%.*]] to <3 x i32>
1582 ; VI-NEXT: [[TMP2:%.*]] = zext <3 x i15> [[B:%.*]] to <3 x i32>
1583 ; VI-NEXT: [[TMP3:%.*]] = sub nuw nsw <3 x i32> [[TMP1]], [[TMP2]]
1584 ; VI-NEXT: [[TMP4:%.*]] = trunc <3 x i32> [[TMP3]] to <3 x i15>
1585 ; VI-NEXT: store volatile <3 x i15> [[TMP4]], <3 x i15> addrspace(1)* undef
1586 ; VI-NEXT: ret void
1599 ; VI-LABEL: @sub_nuw_nsw_3xi15(
1600 ; VI-NEXT: [[TMP1:%.*]] = zext <3 x i15> [[A:%.*]] to <3 x i32>
1601 ; VI-NEXT: [[TMP2:%.*]] = zext <3 x i15> [[B:%.*]] to <3 x i32>
1602 ; VI-NEXT: [[TMP3:%.*]] = sub nuw nsw <3 x i32> [[TMP1]], [[TMP2]]
1603 ; VI-NEXT: [[TMP4:%.*]] = trunc <3 x i32> [[TMP3]] to <3 x i15>
1604 ; VI-NEXT: store volatile <3 x i15> [[TMP4]], <3 x i15> addrspace(1)* undef
1605 ; VI-NEXT: ret void
1618 ; VI-LABEL: @mul_3xi15(
1619 ; VI-NEXT: [[TMP1:%.*]] = zext <3 x i15> [[A:%.*]] to <3 x i32>
1620 ; VI-NEXT: [[TMP2:%.*]] = zext <3 x i15> [[B:%.*]] to <3 x i32>
1621 ; VI-NEXT: [[TMP3:%.*]] = mul nuw <3 x i32> [[TMP1]], [[TMP2]]
1622 ; VI-NEXT: [[TMP4:%.*]] = trunc <3 x i32> [[TMP3]] to <3 x i15>
1623 ; VI-NEXT: store volatile <3 x i15> [[TMP4]], <3 x i15> addrspace(1)* undef
1624 ; VI-NEXT: ret void
1637 ; VI-LABEL: @mul_nsw_3xi15(
1638 ; VI-NEXT: [[TMP1:%.*]] = zext <3 x i15> [[A:%.*]] to <3 x i32>
1639 ; VI-NEXT: [[TMP2:%.*]] = zext <3 x i15> [[B:%.*]] to <3 x i32>
1640 ; VI-NEXT: [[TMP3:%.*]] = mul nuw <3 x i32> [[TMP1]], [[TMP2]]
1641 ; VI-NEXT: [[TMP4:%.*]] = trunc <3 x i32> [[TMP3]] to <3 x i15>
1642 ; VI-NEXT: store volatile <3 x i15> [[TMP4]], <3 x i15> addrspace(1)* undef
1643 ; VI-NEXT: ret void
1656 ; VI-LABEL: @mul_nuw_3xi15(
1657 ; VI-NEXT: [[TMP1:%.*]] = zext <3 x i15> [[A:%.*]] to <3 x i32>
1658 ; VI-NEXT: [[TMP2:%.*]] = zext <3 x i15> [[B:%.*]] to <3 x i32>
1659 ; VI-NEXT: [[TMP3:%.*]] = mul nuw nsw <3 x i32> [[TMP1]], [[TMP2]]
1660 ; VI-NEXT: [[TMP4:%.*]] = trunc <3 x i32> [[TMP3]] to <3 x i15>
1661 ; VI-NEXT: store volatile <3 x i15> [[TMP4]], <3 x i15> addrspace(1)* undef
1662 ; VI-NEXT: ret void
1675 ; VI-LABEL: @mul_nuw_nsw_3xi15(
1676 ; VI-NEXT: [[TMP1:%.*]] = zext <3 x i15> [[A:%.*]] to <3 x i32>
1677 ; VI-NEXT: [[TMP2:%.*]] = zext <3 x i15> [[B:%.*]] to <3 x i32>
1678 ; VI-NEXT: [[TMP3:%.*]] = mul nuw nsw <3 x i32> [[TMP1]], [[TMP2]]
1679 ; VI-NEXT: [[TMP4:%.*]] = trunc <3 x i32> [[TMP3]] to <3 x i15>
1680 ; VI-NEXT: store volatile <3 x i15> [[TMP4]], <3 x i15> addrspace(1)* undef
1681 ; VI-NEXT: ret void
1694 ; VI-LABEL: @shl_3xi15(
1695 ; VI-NEXT: [[TMP1:%.*]] = zext <3 x i15> [[A:%.*]] to <3 x i32>
1696 ; VI-NEXT: [[TMP2:%.*]] = zext <3 x i15> [[B:%.*]] to <3 x i32>
1697 ; VI-NEXT: [[TMP3:%.*]] = shl nuw nsw <3 x i32> [[TMP1]], [[TMP2]]
1698 ; VI-NEXT: [[TMP4:%.*]] = trunc <3 x i32> [[TMP3]] to <3 x i15>
1699 ; VI-NEXT: store volatile <3 x i15> [[TMP4]], <3 x i15> addrspace(1)* undef
1700 ; VI-NEXT: ret void
1713 ; VI-LABEL: @shl_nsw_3xi15(
1714 ; VI-NEXT: [[TMP1:%.*]] = zext <3 x i15> [[A:%.*]] to <3 x i32>
1715 ; VI-NEXT: [[TMP2:%.*]] = zext <3 x i15> [[B:%.*]] to <3 x i32>
1716 ; VI-NEXT: [[TMP3:%.*]] = shl nuw nsw <3 x i32> [[TMP1]], [[TMP2]]
1717 ; VI-NEXT: [[TMP4:%.*]] = trunc <3 x i32> [[TMP3]] to <3 x i15>
1718 ; VI-NEXT: store volatile <3 x i15> [[TMP4]], <3 x i15> addrspace(1)* undef
1719 ; VI-NEXT: ret void
1732 ; VI-LABEL: @shl_nuw_3xi15(
1733 ; VI-NEXT: [[TMP1:%.*]] = zext <3 x i15> [[A:%.*]] to <3 x i32>
1734 ; VI-NEXT: [[TMP2:%.*]] = zext <3 x i15> [[B:%.*]] to <3 x i32>
1735 ; VI-NEXT: [[TMP3:%.*]] = shl nuw nsw <3 x i32> [[TMP1]], [[TMP2]]
1736 ; VI-NEXT: [[TMP4:%.*]] = trunc <3 x i32> [[TMP3]] to <3 x i15>
1737 ; VI-NEXT: store volatile <3 x i15> [[TMP4]], <3 x i15> addrspace(1)* undef
1738 ; VI-NEXT: ret void
1751 ; VI-LABEL: @shl_nuw_nsw_3xi15(
1752 ; VI-NEXT: [[TMP1:%.*]] = zext <3 x i15> [[A:%.*]] to <3 x i32>
1753 ; VI-NEXT: [[TMP2:%.*]] = zext <3 x i15> [[B:%.*]] to <3 x i32>
1754 ; VI-NEXT: [[TMP3:%.*]] = shl nuw nsw <3 x i32> [[TMP1]], [[TMP2]]
1755 ; VI-NEXT: [[TMP4:%.*]] = trunc <3 x i32> [[TMP3]] to <3 x i15>
1756 ; VI-NEXT: store volatile <3 x i15> [[TMP4]], <3 x i15> addrspace(1)* undef
1757 ; VI-NEXT: ret void
1770 ; VI-LABEL: @lshr_3xi15(
1771 ; VI-NEXT: [[TMP1:%.*]] = zext <3 x i15> [[A:%.*]] to <3 x i32>
1772 ; VI-NEXT: [[TMP2:%.*]] = zext <3 x i15> [[B:%.*]] to <3 x i32>
1773 ; VI-NEXT: [[TMP3:%.*]] = lshr <3 x i32> [[TMP1]], [[TMP2]]
1774 ; VI-NEXT: [[TMP4:%.*]] = trunc <3 x i32> [[TMP3]] to <3 x i15>
1775 ; VI-NEXT: store volatile <3 x i15> [[TMP4]], <3 x i15> addrspace(1)* undef
1776 ; VI-NEXT: ret void
1789 ; VI-LABEL: @lshr_exact_3xi15(
1790 ; VI-NEXT: [[TMP1:%.*]] = zext <3 x i15> [[A:%.*]] to <3 x i32>
1791 ; VI-NEXT: [[TMP2:%.*]] = zext <3 x i15> [[B:%.*]] to <3 x i32>
1792 ; VI-NEXT: [[TMP3:%.*]] = lshr exact <3 x i32> [[TMP1]], [[TMP2]]
1793 ; VI-NEXT: [[TMP4:%.*]] = trunc <3 x i32> [[TMP3]] to <3 x i15>
1794 ; VI-NEXT: store volatile <3 x i15> [[TMP4]], <3 x i15> addrspace(1)* undef
1795 ; VI-NEXT: ret void
1808 ; VI-LABEL: @ashr_3xi15(
1809 ; VI-NEXT: [[TMP1:%.*]] = sext <3 x i15> [[A:%.*]] to <3 x i32>
1810 ; VI-NEXT: [[TMP2:%.*]] = sext <3 x i15> [[B:%.*]] to <3 x i32>
1811 ; VI-NEXT: [[TMP3:%.*]] = ashr <3 x i32> [[TMP1]], [[TMP2]]
1812 ; VI-NEXT: [[TMP4:%.*]] = trunc <3 x i32> [[TMP3]] to <3 x i15>
1813 ; VI-NEXT: store volatile <3 x i15> [[TMP4]], <3 x i15> addrspace(1)* undef
1814 ; VI-NEXT: ret void
1827 ; VI-LABEL: @ashr_exact_3xi15(
1828 ; VI-NEXT: [[TMP1:%.*]] = sext <3 x i15> [[A:%.*]] to <3 x i32>
1829 ; VI-NEXT: [[TMP2:%.*]] = sext <3 x i15> [[B:%.*]] to <3 x i32>
1830 ; VI-NEXT: [[TMP3:%.*]] = ashr exact <3 x i32> [[TMP1]], [[TMP2]]
1831 ; VI-NEXT: [[TMP4:%.*]] = trunc <3 x i32> [[TMP3]] to <3 x i15>
1832 ; VI-NEXT: store volatile <3 x i15> [[TMP4]], <3 x i15> addrspace(1)* undef
1833 ; VI-NEXT: ret void
1846 ; VI-LABEL: @and_3xi15(
1847 ; VI-NEXT: [[TMP1:%.*]] = zext <3 x i15> [[A:%.*]] to <3 x i32>
1848 ; VI-NEXT: [[TMP2:%.*]] = zext <3 x i15> [[B:%.*]] to <3 x i32>
1849 ; VI-NEXT: [[TMP3:%.*]] = and <3 x i32> [[TMP1]], [[TMP2]]
1850 ; VI-NEXT: [[TMP4:%.*]] = trunc <3 x i32> [[TMP3]] to <3 x i15>
1851 ; VI-NEXT: store volatile <3 x i15> [[TMP4]], <3 x i15> addrspace(1)* undef
1852 ; VI-NEXT: ret void
1865 ; VI-LABEL: @or_3xi15(
1866 ; VI-NEXT: [[TMP1:%.*]] = zext <3 x i15> [[A:%.*]] to <3 x i32>
1867 ; VI-NEXT: [[TMP2:%.*]] = zext <3 x i15> [[B:%.*]] to <3 x i32>
1868 ; VI-NEXT: [[TMP3:%.*]] = or <3 x i32> [[TMP1]], [[TMP2]]
1869 ; VI-NEXT: [[TMP4:%.*]] = trunc <3 x i32> [[TMP3]] to <3 x i15>
1870 ; VI-NEXT: store volatile <3 x i15> [[TMP4]], <3 x i15> addrspace(1)* undef
1871 ; VI-NEXT: ret void
1884 ; VI-LABEL: @xor_3xi15(
1885 ; VI-NEXT: [[TMP1:%.*]] = zext <3 x i15> [[A:%.*]] to <3 x i32>
1886 ; VI-NEXT: [[TMP2:%.*]] = zext <3 x i15> [[B:%.*]] to <3 x i32>
1887 ; VI-NEXT: [[TMP3:%.*]] = xor <3 x i32> [[TMP1]], [[TMP2]]
1888 ; VI-NEXT: [[TMP4:%.*]] = trunc <3 x i32> [[TMP3]] to <3 x i15>
1889 ; VI-NEXT: store volatile <3 x i15> [[TMP4]], <3 x i15> addrspace(1)* undef
1890 ; VI-NEXT: ret void
1904 ; VI-LABEL: @select_eq_3xi15(
1905 ; VI-NEXT: [[TMP1:%.*]] = zext <3 x i15> [[A:%.*]] to <3 x i32>
1906 ; VI-NEXT: [[TMP2:%.*]] = zext <3 x i15> [[B:%.*]] to <3 x i32>
1907 ; VI-NEXT: [[TMP3:%.*]] = icmp eq <3 x i32> [[TMP1]], [[TMP2]]
1908 ; VI-NEXT: [[TMP4:%.*]] = zext <3 x i15> [[A]] to <3 x i32>
1909 ; VI-NEXT: [[TMP5:%.*]] = zext <3 x i15> [[B]] to <3 x i32>
1910 ; VI-NEXT: [[TMP6:%.*]] = select <3 x i1> [[TMP3]], <3 x i32> [[TMP4]], <3 x i32> [[TMP5]]
1911 ; VI-NEXT: [[TMP7:%.*]] = trunc <3 x i32> [[TMP6]] to <3 x i15>
1912 ; VI-NEXT: store volatile <3 x i15> [[TMP7]], <3 x i15> addrspace(1)* undef
1913 ; VI-NEXT: ret void
1928 ; VI-LABEL: @select_ne_3xi15(
1929 ; VI-NEXT: [[TMP1:%.*]] = zext <3 x i15> [[A:%.*]] to <3 x i32>
1930 ; VI-NEXT: [[TMP2:%.*]] = zext <3 x i15> [[B:%.*]] to <3 x i32>
1931 ; VI-NEXT: [[TMP3:%.*]] = icmp ne <3 x i32> [[TMP1]], [[TMP2]]
1932 ; VI-NEXT: [[TMP4:%.*]] = zext <3 x i15> [[A]] to <3 x i32>
1933 ; VI-NEXT: [[TMP5:%.*]] = zext <3 x i15> [[B]] to <3 x i32>
1934 ; VI-NEXT: [[TMP6:%.*]] = select <3 x i1> [[TMP3]], <3 x i32> [[TMP4]], <3 x i32> [[TMP5]]
1935 ; VI-NEXT: [[TMP7:%.*]] = trunc <3 x i32> [[TMP6]] to <3 x i15>
1936 ; VI-NEXT: store volatile <3 x i15> [[TMP7]], <3 x i15> addrspace(1)* undef
1937 ; VI-NEXT: ret void
1952 ; VI-LABEL: @select_ugt_3xi15(
1953 ; VI-NEXT: [[TMP1:%.*]] = zext <3 x i15> [[A:%.*]] to <3 x i32>
1954 ; VI-NEXT: [[TMP2:%.*]] = zext <3 x i15> [[B:%.*]] to <3 x i32>
1955 ; VI-NEXT: [[TMP3:%.*]] = icmp ugt <3 x i32> [[TMP1]], [[TMP2]]
1956 ; VI-NEXT: [[TMP4:%.*]] = zext <3 x i15> [[A]] to <3 x i32>
1957 ; VI-NEXT: [[TMP5:%.*]] = zext <3 x i15> [[B]] to <3 x i32>
1958 ; VI-NEXT: [[TMP6:%.*]] = select <3 x i1> [[TMP3]], <3 x i32> [[TMP4]], <3 x i32> [[TMP5]]
1959 ; VI-NEXT: [[TMP7:%.*]] = trunc <3 x i32> [[TMP6]] to <3 x i15>
1960 ; VI-NEXT: store volatile <3 x i15> [[TMP7]], <3 x i15> addrspace(1)* undef
1961 ; VI-NEXT: ret void
1976 ; VI-LABEL: @select_uge_3xi15(
1977 ; VI-NEXT: [[TMP1:%.*]] = zext <3 x i15> [[A:%.*]] to <3 x i32>
1978 ; VI-NEXT: [[TMP2:%.*]] = zext <3 x i15> [[B:%.*]] to <3 x i32>
1979 ; VI-NEXT: [[TMP3:%.*]] = icmp uge <3 x i32> [[TMP1]], [[TMP2]]
1980 ; VI-NEXT: [[TMP4:%.*]] = zext <3 x i15> [[A]] to <3 x i32>
1981 ; VI-NEXT: [[TMP5:%.*]] = zext <3 x i15> [[B]] to <3 x i32>
1982 ; VI-NEXT: [[TMP6:%.*]] = select <3 x i1> [[TMP3]], <3 x i32> [[TMP4]], <3 x i32> [[TMP5]]
1983 ; VI-NEXT: [[TMP7:%.*]] = trunc <3 x i32> [[TMP6]] to <3 x i15>
1984 ; VI-NEXT: store volatile <3 x i15> [[TMP7]], <3 x i15> addrspace(1)* undef
1985 ; VI-NEXT: ret void
2000 ; VI-LABEL: @select_ult_3xi15(
2001 ; VI-NEXT: [[TMP1:%.*]] = zext <3 x i15> [[A:%.*]] to <3 x i32>
2002 ; VI-NEXT: [[TMP2:%.*]] = zext <3 x i15> [[B:%.*]] to <3 x i32>
2003 ; VI-NEXT: [[TMP3:%.*]] = icmp ult <3 x i32> [[TMP1]], [[TMP2]]
2004 ; VI-NEXT: [[TMP4:%.*]] = zext <3 x i15> [[A]] to <3 x i32>
2005 ; VI-NEXT: [[TMP5:%.*]] = zext <3 x i15> [[B]] to <3 x i32>
2006 ; VI-NEXT: [[TMP6:%.*]] = select <3 x i1> [[TMP3]], <3 x i32> [[TMP4]], <3 x i32> [[TMP5]]
2007 ; VI-NEXT: [[TMP7:%.*]] = trunc <3 x i32> [[TMP6]] to <3 x i15>
2008 ; VI-NEXT: store volatile <3 x i15> [[TMP7]], <3 x i15> addrspace(1)* undef
2009 ; VI-NEXT: ret void
2024 ; VI-LABEL: @select_ule_3xi15(
2025 ; VI-NEXT: [[TMP1:%.*]] = zext <3 x i15> [[A:%.*]] to <3 x i32>
2026 ; VI-NEXT: [[TMP2:%.*]] = zext <3 x i15> [[B:%.*]] to <3 x i32>
2027 ; VI-NEXT: [[TMP3:%.*]] = icmp ule <3 x i32> [[TMP1]], [[TMP2]]
2028 ; VI-NEXT: [[TMP4:%.*]] = zext <3 x i15> [[A]] to <3 x i32>
2029 ; VI-NEXT: [[TMP5:%.*]] = zext <3 x i15> [[B]] to <3 x i32>
2030 ; VI-NEXT: [[TMP6:%.*]] = select <3 x i1> [[TMP3]], <3 x i32> [[TMP4]], <3 x i32> [[TMP5]]
2031 ; VI-NEXT: [[TMP7:%.*]] = trunc <3 x i32> [[TMP6]] to <3 x i15>
2032 ; VI-NEXT: store volatile <3 x i15> [[TMP7]], <3 x i15> addrspace(1)* undef
2033 ; VI-NEXT: ret void
2048 ; VI-LABEL: @select_sgt_3xi15(
2049 ; VI-NEXT: [[TMP1:%.*]] = sext <3 x i15> [[A:%.*]] to <3 x i32>
2050 ; VI-NEXT: [[TMP2:%.*]] = sext <3 x i15> [[B:%.*]] to <3 x i32>
2051 ; VI-NEXT: [[TMP3:%.*]] = icmp sgt <3 x i32> [[TMP1]], [[TMP2]]
2052 ; VI-NEXT: [[TMP4:%.*]] = sext <3 x i15> [[A]] to <3 x i32>
2053 ; VI-NEXT: [[TMP5:%.*]] = sext <3 x i15> [[B]] to <3 x i32>
2054 ; VI-NEXT: [[TMP6:%.*]] = select <3 x i1> [[TMP3]], <3 x i32> [[TMP4]], <3 x i32> [[TMP5]]
2055 ; VI-NEXT: [[TMP7:%.*]] = trunc <3 x i32> [[TMP6]] to <3 x i15>
2056 ; VI-NEXT: store volatile <3 x i15> [[TMP7]], <3 x i15> addrspace(1)* undef
2057 ; VI-NEXT: ret void
2072 ; VI-LABEL: @select_sge_3xi15(
2073 ; VI-NEXT: [[TMP1:%.*]] = sext <3 x i15> [[A:%.*]] to <3 x i32>
2074 ; VI-NEXT: [[TMP2:%.*]] = sext <3 x i15> [[B:%.*]] to <3 x i32>
2075 ; VI-NEXT: [[TMP3:%.*]] = icmp sge <3 x i32> [[TMP1]], [[TMP2]]
2076 ; VI-NEXT: [[TMP4:%.*]] = sext <3 x i15> [[A]] to <3 x i32>
2077 ; VI-NEXT: [[TMP5:%.*]] = sext <3 x i15> [[B]] to <3 x i32>
2078 ; VI-NEXT: [[TMP6:%.*]] = select <3 x i1> [[TMP3]], <3 x i32> [[TMP4]], <3 x i32> [[TMP5]]
2079 ; VI-NEXT: [[TMP7:%.*]] = trunc <3 x i32> [[TMP6]] to <3 x i15>
2080 ; VI-NEXT: store volatile <3 x i15> [[TMP7]], <3 x i15> addrspace(1)* undef
2081 ; VI-NEXT: ret void
2096 ; VI-LABEL: @select_slt_3xi15(
2097 ; VI-NEXT: [[TMP1:%.*]] = sext <3 x i15> [[A:%.*]] to <3 x i32>
2098 ; VI-NEXT: [[TMP2:%.*]] = sext <3 x i15> [[B:%.*]] to <3 x i32>
2099 ; VI-NEXT: [[TMP3:%.*]] = icmp slt <3 x i32> [[TMP1]], [[TMP2]]
2100 ; VI-NEXT: [[TMP4:%.*]] = sext <3 x i15> [[A]] to <3 x i32>
2101 ; VI-NEXT: [[TMP5:%.*]] = sext <3 x i15> [[B]] to <3 x i32>
2102 ; VI-NEXT: [[TMP6:%.*]] = select <3 x i1> [[TMP3]], <3 x i32> [[TMP4]], <3 x i32> [[TMP5]]
2103 ; VI-NEXT: [[TMP7:%.*]] = trunc <3 x i32> [[TMP6]] to <3 x i15>
2104 ; VI-NEXT: store volatile <3 x i15> [[TMP7]], <3 x i15> addrspace(1)* undef
2105 ; VI-NEXT: ret void
2120 ; VI-LABEL: @select_sle_3xi15(
2121 ; VI-NEXT: [[TMP1:%.*]] = sext <3 x i15> [[A:%.*]] to <3 x i32>
2122 ; VI-NEXT: [[TMP2:%.*]] = sext <3 x i15> [[B:%.*]] to <3 x i32>
2123 ; VI-NEXT: [[TMP3:%.*]] = icmp sle <3 x i32> [[TMP1]], [[TMP2]]
2124 ; VI-NEXT: [[TMP4:%.*]] = sext <3 x i15> [[A]] to <3 x i32>
2125 ; VI-NEXT: [[TMP5:%.*]] = sext <3 x i15> [[B]] to <3 x i32>
2126 ; VI-NEXT: [[TMP6:%.*]] = select <3 x i1> [[TMP3]], <3 x i32> [[TMP4]], <3 x i32> [[TMP5]]
2127 ; VI-NEXT: [[TMP7:%.*]] = trunc <3 x i32> [[TMP6]] to <3 x i15>
2128 ; VI-NEXT: store volatile <3 x i15> [[TMP7]], <3 x i15> addrspace(1)* undef
2129 ; VI-NEXT: ret void
2144 ; VI-LABEL: @bitreverse_3xi15(
2145 ; VI-NEXT: [[TMP1:%.*]] = zext <3 x i15> [[A:%.*]] to <3 x i32>
2146 ; VI-NEXT: [[TMP2:%.*]] = call <3 x i32> @llvm.bitreverse.v3i32(<3 x i32> [[TMP1]])
2147 ; VI-NEXT: [[TMP3:%.*]] = lshr <3 x i32> [[TMP2]], <i32 17, i32 17, i32 17>
2148 ; VI-NEXT: [[TMP4:%.*]] = trunc <3 x i32> [[TMP3]] to <3 x i15>
2149 ; VI-NEXT: store volatile <3 x i15> [[TMP4]], <3 x i15> addrspace(1)* undef
2150 ; VI-NEXT: ret void
2163 ; VI-LABEL: @add_3xi16(
2164 ; VI-NEXT: [[TMP1:%.*]] = zext <3 x i16> [[A:%.*]] to <3 x i32>
2165 ; VI-NEXT: [[TMP2:%.*]] = zext <3 x i16> [[B:%.*]] to <3 x i32>
2166 ; VI-NEXT: [[TMP3:%.*]] = add nuw nsw <3 x i32> [[TMP1]], [[TMP2]]
2167 ; VI-NEXT: [[TMP4:%.*]] = trunc <3 x i32> [[TMP3]] to <3 x i16>
2168 ; VI-NEXT: store volatile <3 x i16> [[TMP4]], <3 x i16> addrspace(1)* undef
2169 ; VI-NEXT: ret void
2182 ; VI-LABEL: @add_nsw_3xi16(
2183 ; VI-NEXT: [[TMP1:%.*]] = zext <3 x i16> [[A:%.*]] to <3 x i32>
2184 ; VI-NEXT: [[TMP2:%.*]] = zext <3 x i16> [[B:%.*]] to <3 x i32>
2185 ; VI-NEXT: [[TMP3:%.*]] = add nuw nsw <3 x i32> [[TMP1]], [[TMP2]]
2186 ; VI-NEXT: [[TMP4:%.*]] = trunc <3 x i32> [[TMP3]] to <3 x i16>
2187 ; VI-NEXT: store volatile <3 x i16> [[TMP4]], <3 x i16> addrspace(1)* undef
2188 ; VI-NEXT: ret void
2201 ; VI-LABEL: @add_nuw_3xi16(
2202 ; VI-NEXT: [[TMP1:%.*]] = zext <3 x i16> [[A:%.*]] to <3 x i32>
2203 ; VI-NEXT: [[TMP2:%.*]] = zext <3 x i16> [[B:%.*]] to <3 x i32>
2204 ; VI-NEXT: [[TMP3:%.*]] = add nuw nsw <3 x i32> [[TMP1]], [[TMP2]]
2205 ; VI-NEXT: [[TMP4:%.*]] = trunc <3 x i32> [[TMP3]] to <3 x i16>
2206 ; VI-NEXT: store volatile <3 x i16> [[TMP4]], <3 x i16> addrspace(1)* undef
2207 ; VI-NEXT: ret void
2220 ; VI-LABEL: @add_nuw_nsw_3xi16(
2221 ; VI-NEXT: [[TMP1:%.*]] = zext <3 x i16> [[A:%.*]] to <3 x i32>
2222 ; VI-NEXT: [[TMP2:%.*]] = zext <3 x i16> [[B:%.*]] to <3 x i32>
2223 ; VI-NEXT: [[TMP3:%.*]] = add nuw nsw <3 x i32> [[TMP1]], [[TMP2]]
2224 ; VI-NEXT: [[TMP4:%.*]] = trunc <3 x i32> [[TMP3]] to <3 x i16>
2225 ; VI-NEXT: store volatile <3 x i16> [[TMP4]], <3 x i16> addrspace(1)* undef
2226 ; VI-NEXT: ret void
2239 ; VI-LABEL: @sub_3xi16(
2240 ; VI-NEXT: [[TMP1:%.*]] = zext <3 x i16> [[A:%.*]] to <3 x i32>
2241 ; VI-NEXT: [[TMP2:%.*]] = zext <3 x i16> [[B:%.*]] to <3 x i32>
2242 ; VI-NEXT: [[TMP3:%.*]] = sub nsw <3 x i32> [[TMP1]], [[TMP2]]
2243 ; VI-NEXT: [[TMP4:%.*]] = trunc <3 x i32> [[TMP3]] to <3 x i16>
2244 ; VI-NEXT: store volatile <3 x i16> [[TMP4]], <3 x i16> addrspace(1)* undef
2245 ; VI-NEXT: ret void
2258 ; VI-LABEL: @sub_nsw_3xi16(
2259 ; VI-NEXT: [[TMP1:%.*]] = zext <3 x i16> [[A:%.*]] to <3 x i32>
2260 ; VI-NEXT: [[TMP2:%.*]] = zext <3 x i16> [[B:%.*]] to <3 x i32>
2261 ; VI-NEXT: [[TMP3:%.*]] = sub nsw <3 x i32> [[TMP1]], [[TMP2]]
2262 ; VI-NEXT: [[TMP4:%.*]] = trunc <3 x i32> [[TMP3]] to <3 x i16>
2263 ; VI-NEXT: store volatile <3 x i16> [[TMP4]], <3 x i16> addrspace(1)* undef
2264 ; VI-NEXT: ret void
2277 ; VI-LABEL: @sub_nuw_3xi16(
2278 ; VI-NEXT: [[TMP1:%.*]] = zext <3 x i16> [[A:%.*]] to <3 x i32>
2279 ; VI-NEXT: [[TMP2:%.*]] = zext <3 x i16> [[B:%.*]] to <3 x i32>
2280 ; VI-NEXT: [[TMP3:%.*]] = sub nuw nsw <3 x i32> [[TMP1]], [[TMP2]]
2281 ; VI-NEXT: [[TMP4:%.*]] = trunc <3 x i32> [[TMP3]] to <3 x i16>
2282 ; VI-NEXT: store volatile <3 x i16> [[TMP4]], <3 x i16> addrspace(1)* undef
2283 ; VI-NEXT: ret void
2296 ; VI-LABEL: @sub_nuw_nsw_3xi16(
2297 ; VI-NEXT: [[TMP1:%.*]] = zext <3 x i16> [[A:%.*]] to <3 x i32>
2298 ; VI-NEXT: [[TMP2:%.*]] = zext <3 x i16> [[B:%.*]] to <3 x i32>
2299 ; VI-NEXT: [[TMP3:%.*]] = sub nuw nsw <3 x i32> [[TMP1]], [[TMP2]]
2300 ; VI-NEXT: [[TMP4:%.*]] = trunc <3 x i32> [[TMP3]] to <3 x i16>
2301 ; VI-NEXT: store volatile <3 x i16> [[TMP4]], <3 x i16> addrspace(1)* undef
2302 ; VI-NEXT: ret void
2315 ; VI-LABEL: @mul_3xi16(
2316 ; VI-NEXT: [[TMP1:%.*]] = zext <3 x i16> [[A:%.*]] to <3 x i32>
2317 ; VI-NEXT: [[TMP2:%.*]] = zext <3 x i16> [[B:%.*]] to <3 x i32>
2318 ; VI-NEXT: [[TMP3:%.*]] = mul nuw <3 x i32> [[TMP1]], [[TMP2]]
2319 ; VI-NEXT: [[TMP4:%.*]] = trunc <3 x i32> [[TMP3]] to <3 x i16>
2320 ; VI-NEXT: store volatile <3 x i16> [[TMP4]], <3 x i16> addrspace(1)* undef
2321 ; VI-NEXT: ret void
2334 ; VI-LABEL: @mul_nsw_3xi16(
2335 ; VI-NEXT: [[TMP1:%.*]] = zext <3 x i16> [[A:%.*]] to <3 x i32>
2336 ; VI-NEXT: [[TMP2:%.*]] = zext <3 x i16> [[B:%.*]] to <3 x i32>
2337 ; VI-NEXT: [[TMP3:%.*]] = mul nuw <3 x i32> [[TMP1]], [[TMP2]]
2338 ; VI-NEXT: [[TMP4:%.*]] = trunc <3 x i32> [[TMP3]] to <3 x i16>
2339 ; VI-NEXT: store volatile <3 x i16> [[TMP4]], <3 x i16> addrspace(1)* undef
2340 ; VI-NEXT: ret void
2353 ; VI-LABEL: @mul_nuw_3xi16(
2354 ; VI-NEXT: [[TMP1:%.*]] = zext <3 x i16> [[A:%.*]] to <3 x i32>
2355 ; VI-NEXT: [[TMP2:%.*]] = zext <3 x i16> [[B:%.*]] to <3 x i32>
2356 ; VI-NEXT: [[TMP3:%.*]] = mul nuw nsw <3 x i32> [[TMP1]], [[TMP2]]
2357 ; VI-NEXT: [[TMP4:%.*]] = trunc <3 x i32> [[TMP3]] to <3 x i16>
2358 ; VI-NEXT: store volatile <3 x i16> [[TMP4]], <3 x i16> addrspace(1)* undef
2359 ; VI-NEXT: ret void
2372 ; VI-LABEL: @mul_nuw_nsw_3xi16(
2373 ; VI-NEXT: [[TMP1:%.*]] = zext <3 x i16> [[A:%.*]] to <3 x i32>
2374 ; VI-NEXT: [[TMP2:%.*]] = zext <3 x i16> [[B:%.*]] to <3 x i32>
2375 ; VI-NEXT: [[TMP3:%.*]] = mul nuw nsw <3 x i32> [[TMP1]], [[TMP2]]
2376 ; VI-NEXT: [[TMP4:%.*]] = trunc <3 x i32> [[TMP3]] to <3 x i16>
2377 ; VI-NEXT: store volatile <3 x i16> [[TMP4]], <3 x i16> addrspace(1)* undef
2378 ; VI-NEXT: ret void
2391 ; VI-LABEL: @shl_3xi16(
2392 ; VI-NEXT: [[TMP1:%.*]] = zext <3 x i16> [[A:%.*]] to <3 x i32>
2393 ; VI-NEXT: [[TMP2:%.*]] = zext <3 x i16> [[B:%.*]] to <3 x i32>
2394 ; VI-NEXT: [[TMP3:%.*]] = shl nuw nsw <3 x i32> [[TMP1]], [[TMP2]]
2395 ; VI-NEXT: [[TMP4:%.*]] = trunc <3 x i32> [[TMP3]] to <3 x i16>
2396 ; VI-NEXT: store volatile <3 x i16> [[TMP4]], <3 x i16> addrspace(1)* undef
2397 ; VI-NEXT: ret void
2410 ; VI-LABEL: @shl_nsw_3xi16(
2411 ; VI-NEXT: [[TMP1:%.*]] = zext <3 x i16> [[A:%.*]] to <3 x i32>
2412 ; VI-NEXT: [[TMP2:%.*]] = zext <3 x i16> [[B:%.*]] to <3 x i32>
2413 ; VI-NEXT: [[TMP3:%.*]] = shl nuw nsw <3 x i32> [[TMP1]], [[TMP2]]
2414 ; VI-NEXT: [[TMP4:%.*]] = trunc <3 x i32> [[TMP3]] to <3 x i16>
2415 ; VI-NEXT: store volatile <3 x i16> [[TMP4]], <3 x i16> addrspace(1)* undef
2416 ; VI-NEXT: ret void
2429 ; VI-LABEL: @shl_nuw_3xi16(
2430 ; VI-NEXT: [[TMP1:%.*]] = zext <3 x i16> [[A:%.*]] to <3 x i32>
2431 ; VI-NEXT: [[TMP2:%.*]] = zext <3 x i16> [[B:%.*]] to <3 x i32>
2432 ; VI-NEXT: [[TMP3:%.*]] = shl nuw nsw <3 x i32> [[TMP1]], [[TMP2]]
2433 ; VI-NEXT: [[TMP4:%.*]] = trunc <3 x i32> [[TMP3]] to <3 x i16>
2434 ; VI-NEXT: store volatile <3 x i16> [[TMP4]], <3 x i16> addrspace(1)* undef
2435 ; VI-NEXT: ret void
2448 ; VI-LABEL: @shl_nuw_nsw_3xi16(
2449 ; VI-NEXT: [[TMP1:%.*]] = zext <3 x i16> [[A:%.*]] to <3 x i32>
2450 ; VI-NEXT: [[TMP2:%.*]] = zext <3 x i16> [[B:%.*]] to <3 x i32>
2451 ; VI-NEXT: [[TMP3:%.*]] = shl nuw nsw <3 x i32> [[TMP1]], [[TMP2]]
2452 ; VI-NEXT: [[TMP4:%.*]] = trunc <3 x i32> [[TMP3]] to <3 x i16>
2453 ; VI-NEXT: store volatile <3 x i16> [[TMP4]], <3 x i16> addrspace(1)* undef
2454 ; VI-NEXT: ret void
2467 ; VI-LABEL: @lshr_3xi16(
2468 ; VI-NEXT: [[TMP1:%.*]] = zext <3 x i16> [[A:%.*]] to <3 x i32>
2469 ; VI-NEXT: [[TMP2:%.*]] = zext <3 x i16> [[B:%.*]] to <3 x i32>
2470 ; VI-NEXT: [[TMP3:%.*]] = lshr <3 x i32> [[TMP1]], [[TMP2]]
2471 ; VI-NEXT: [[TMP4:%.*]] = trunc <3 x i32> [[TMP3]] to <3 x i16>
2472 ; VI-NEXT: store volatile <3 x i16> [[TMP4]], <3 x i16> addrspace(1)* undef
2473 ; VI-NEXT: ret void
2486 ; VI-LABEL: @lshr_exact_3xi16(
2487 ; VI-NEXT: [[TMP1:%.*]] = zext <3 x i16> [[A:%.*]] to <3 x i32>
2488 ; VI-NEXT: [[TMP2:%.*]] = zext <3 x i16> [[B:%.*]] to <3 x i32>
2489 ; VI-NEXT: [[TMP3:%.*]] = lshr exact <3 x i32> [[TMP1]], [[TMP2]]
2490 ; VI-NEXT: [[TMP4:%.*]] = trunc <3 x i32> [[TMP3]] to <3 x i16>
2491 ; VI-NEXT: store volatile <3 x i16> [[TMP4]], <3 x i16> addrspace(1)* undef
2492 ; VI-NEXT: ret void
2505 ; VI-LABEL: @ashr_3xi16(
2506 ; VI-NEXT: [[TMP1:%.*]] = sext <3 x i16> [[A:%.*]] to <3 x i32>
2507 ; VI-NEXT: [[TMP2:%.*]] = sext <3 x i16> [[B:%.*]] to <3 x i32>
2508 ; VI-NEXT: [[TMP3:%.*]] = ashr <3 x i32> [[TMP1]], [[TMP2]]
2509 ; VI-NEXT: [[TMP4:%.*]] = trunc <3 x i32> [[TMP3]] to <3 x i16>
2510 ; VI-NEXT: store volatile <3 x i16> [[TMP4]], <3 x i16> addrspace(1)* undef
2511 ; VI-NEXT: ret void
2524 ; VI-LABEL: @ashr_exact_3xi16(
2525 ; VI-NEXT: [[TMP1:%.*]] = sext <3 x i16> [[A:%.*]] to <3 x i32>
2526 ; VI-NEXT: [[TMP2:%.*]] = sext <3 x i16> [[B:%.*]] to <3 x i32>
2527 ; VI-NEXT: [[TMP3:%.*]] = ashr exact <3 x i32> [[TMP1]], [[TMP2]]
2528 ; VI-NEXT: [[TMP4:%.*]] = trunc <3 x i32> [[TMP3]] to <3 x i16>
2529 ; VI-NEXT: store volatile <3 x i16> [[TMP4]], <3 x i16> addrspace(1)* undef
2530 ; VI-NEXT: ret void
2543 ; VI-LABEL: @and_3xi16(
2544 ; VI-NEXT: [[TMP1:%.*]] = zext <3 x i16> [[A:%.*]] to <3 x i32>
2545 ; VI-NEXT: [[TMP2:%.*]] = zext <3 x i16> [[B:%.*]] to <3 x i32>
2546 ; VI-NEXT: [[TMP3:%.*]] = and <3 x i32> [[TMP1]], [[TMP2]]
2547 ; VI-NEXT: [[TMP4:%.*]] = trunc <3 x i32> [[TMP3]] to <3 x i16>
2548 ; VI-NEXT: store volatile <3 x i16> [[TMP4]], <3 x i16> addrspace(1)* undef
2549 ; VI-NEXT: ret void
2562 ; VI-LABEL: @or_3xi16(
2563 ; VI-NEXT: [[TMP1:%.*]] = zext <3 x i16> [[A:%.*]] to <3 x i32>
2564 ; VI-NEXT: [[TMP2:%.*]] = zext <3 x i16> [[B:%.*]] to <3 x i32>
2565 ; VI-NEXT: [[TMP3:%.*]] = or <3 x i32> [[TMP1]], [[TMP2]]
2566 ; VI-NEXT: [[TMP4:%.*]] = trunc <3 x i32> [[TMP3]] to <3 x i16>
2567 ; VI-NEXT: store volatile <3 x i16> [[TMP4]], <3 x i16> addrspace(1)* undef
2568 ; VI-NEXT: ret void
2581 ; VI-LABEL: @xor_3xi16(
2582 ; VI-NEXT: [[TMP1:%.*]] = zext <3 x i16> [[A:%.*]] to <3 x i32>
2583 ; VI-NEXT: [[TMP2:%.*]] = zext <3 x i16> [[B:%.*]] to <3 x i32>
2584 ; VI-NEXT: [[TMP3:%.*]] = xor <3 x i32> [[TMP1]], [[TMP2]]
2585 ; VI-NEXT: [[TMP4:%.*]] = trunc <3 x i32> [[TMP3]] to <3 x i16>
2586 ; VI-NEXT: store volatile <3 x i16> [[TMP4]], <3 x i16> addrspace(1)* undef
2587 ; VI-NEXT: ret void
2601 ; VI-LABEL: @select_eq_3xi16(
2602 ; VI-NEXT: [[TMP1:%.*]] = zext <3 x i16> [[A:%.*]] to <3 x i32>
2603 ; VI-NEXT: [[TMP2:%.*]] = zext <3 x i16> [[B:%.*]] to <3 x i32>
2604 ; VI-NEXT: [[TMP3:%.*]] = icmp eq <3 x i32> [[TMP1]], [[TMP2]]
2605 ; VI-NEXT: [[TMP4:%.*]] = zext <3 x i16> [[A]] to <3 x i32>
2606 ; VI-NEXT: [[TMP5:%.*]] = zext <3 x i16> [[B]] to <3 x i32>
2607 ; VI-NEXT: [[TMP6:%.*]] = select <3 x i1> [[TMP3]], <3 x i32> [[TMP4]], <3 x i32> [[TMP5]]
2608 ; VI-NEXT: [[TMP7:%.*]] = trunc <3 x i32> [[TMP6]] to <3 x i16>
2609 ; VI-NEXT: store volatile <3 x i16> [[TMP7]], <3 x i16> addrspace(1)* undef
2610 ; VI-NEXT: ret void
2625 ; VI-LABEL: @select_ne_3xi16(
2626 ; VI-NEXT: [[TMP1:%.*]] = zext <3 x i16> [[A:%.*]] to <3 x i32>
2627 ; VI-NEXT: [[TMP2:%.*]] = zext <3 x i16> [[B:%.*]] to <3 x i32>
2628 ; VI-NEXT: [[TMP3:%.*]] = icmp ne <3 x i32> [[TMP1]], [[TMP2]]
2629 ; VI-NEXT: [[TMP4:%.*]] = zext <3 x i16> [[A]] to <3 x i32>
2630 ; VI-NEXT: [[TMP5:%.*]] = zext <3 x i16> [[B]] to <3 x i32>
2631 ; VI-NEXT: [[TMP6:%.*]] = select <3 x i1> [[TMP3]], <3 x i32> [[TMP4]], <3 x i32> [[TMP5]]
2632 ; VI-NEXT: [[TMP7:%.*]] = trunc <3 x i32> [[TMP6]] to <3 x i16>
2633 ; VI-NEXT: store volatile <3 x i16> [[TMP7]], <3 x i16> addrspace(1)* undef
2634 ; VI-NEXT: ret void
2649 ; VI-LABEL: @select_ugt_3xi16(
2650 ; VI-NEXT: [[TMP1:%.*]] = zext <3 x i16> [[A:%.*]] to <3 x i32>
2651 ; VI-NEXT: [[TMP2:%.*]] = zext <3 x i16> [[B:%.*]] to <3 x i32>
2652 ; VI-NEXT: [[TMP3:%.*]] = icmp ugt <3 x i32> [[TMP1]], [[TMP2]]
2653 ; VI-NEXT: [[TMP4:%.*]] = zext <3 x i16> [[A]] to <3 x i32>
2654 ; VI-NEXT: [[TMP5:%.*]] = zext <3 x i16> [[B]] to <3 x i32>
2655 ; VI-NEXT: [[TMP6:%.*]] = select <3 x i1> [[TMP3]], <3 x i32> [[TMP4]], <3 x i32> [[TMP5]]
2656 ; VI-NEXT: [[TMP7:%.*]] = trunc <3 x i32> [[TMP6]] to <3 x i16>
2657 ; VI-NEXT: store volatile <3 x i16> [[TMP7]], <3 x i16> addrspace(1)* undef
2658 ; VI-NEXT: ret void
2673 ; VI-LABEL: @select_uge_3xi16(
2674 ; VI-NEXT: [[TMP1:%.*]] = zext <3 x i16> [[A:%.*]] to <3 x i32>
2675 ; VI-NEXT: [[TMP2:%.*]] = zext <3 x i16> [[B:%.*]] to <3 x i32>
2676 ; VI-NEXT: [[TMP3:%.*]] = icmp uge <3 x i32> [[TMP1]], [[TMP2]]
2677 ; VI-NEXT: [[TMP4:%.*]] = zext <3 x i16> [[A]] to <3 x i32>
2678 ; VI-NEXT: [[TMP5:%.*]] = zext <3 x i16> [[B]] to <3 x i32>
2679 ; VI-NEXT: [[TMP6:%.*]] = select <3 x i1> [[TMP3]], <3 x i32> [[TMP4]], <3 x i32> [[TMP5]]
2680 ; VI-NEXT: [[TMP7:%.*]] = trunc <3 x i32> [[TMP6]] to <3 x i16>
2681 ; VI-NEXT: store volatile <3 x i16> [[TMP7]], <3 x i16> addrspace(1)* undef
2682 ; VI-NEXT: ret void
2697 ; VI-LABEL: @select_ult_3xi16(
2698 ; VI-NEXT: [[TMP1:%.*]] = zext <3 x i16> [[A:%.*]] to <3 x i32>
2699 ; VI-NEXT: [[TMP2:%.*]] = zext <3 x i16> [[B:%.*]] to <3 x i32>
2700 ; VI-NEXT: [[TMP3:%.*]] = icmp ult <3 x i32> [[TMP1]], [[TMP2]]
2701 ; VI-NEXT: [[TMP4:%.*]] = zext <3 x i16> [[A]] to <3 x i32>
2702 ; VI-NEXT: [[TMP5:%.*]] = zext <3 x i16> [[B]] to <3 x i32>
2703 ; VI-NEXT: [[TMP6:%.*]] = select <3 x i1> [[TMP3]], <3 x i32> [[TMP4]], <3 x i32> [[TMP5]]
2704 ; VI-NEXT: [[TMP7:%.*]] = trunc <3 x i32> [[TMP6]] to <3 x i16>
2705 ; VI-NEXT: store volatile <3 x i16> [[TMP7]], <3 x i16> addrspace(1)* undef
2706 ; VI-NEXT: ret void
2721 ; VI-LABEL: @select_ule_3xi16(
2722 ; VI-NEXT: [[TMP1:%.*]] = zext <3 x i16> [[A:%.*]] to <3 x i32>
2723 ; VI-NEXT: [[TMP2:%.*]] = zext <3 x i16> [[B:%.*]] to <3 x i32>
2724 ; VI-NEXT: [[TMP3:%.*]] = icmp ule <3 x i32> [[TMP1]], [[TMP2]]
2725 ; VI-NEXT: [[TMP4:%.*]] = zext <3 x i16> [[A]] to <3 x i32>
2726 ; VI-NEXT: [[TMP5:%.*]] = zext <3 x i16> [[B]] to <3 x i32>
2727 ; VI-NEXT: [[TMP6:%.*]] = select <3 x i1> [[TMP3]], <3 x i32> [[TMP4]], <3 x i32> [[TMP5]]
2728 ; VI-NEXT: [[TMP7:%.*]] = trunc <3 x i32> [[TMP6]] to <3 x i16>
2729 ; VI-NEXT: store volatile <3 x i16> [[TMP7]], <3 x i16> addrspace(1)* undef
2730 ; VI-NEXT: ret void
2745 ; VI-LABEL: @select_sgt_3xi16(
2746 ; VI-NEXT: [[TMP1:%.*]] = sext <3 x i16> [[A:%.*]] to <3 x i32>
2747 ; VI-NEXT: [[TMP2:%.*]] = sext <3 x i16> [[B:%.*]] to <3 x i32>
2748 ; VI-NEXT: [[TMP3:%.*]] = icmp sgt <3 x i32> [[TMP1]], [[TMP2]]
2749 ; VI-NEXT: [[TMP4:%.*]] = sext <3 x i16> [[A]] to <3 x i32>
2750 ; VI-NEXT: [[TMP5:%.*]] = sext <3 x i16> [[B]] to <3 x i32>
2751 ; VI-NEXT: [[TMP6:%.*]] = select <3 x i1> [[TMP3]], <3 x i32> [[TMP4]], <3 x i32> [[TMP5]]
2752 ; VI-NEXT: [[TMP7:%.*]] = trunc <3 x i32> [[TMP6]] to <3 x i16>
2753 ; VI-NEXT: store volatile <3 x i16> [[TMP7]], <3 x i16> addrspace(1)* undef
2754 ; VI-NEXT: ret void
2769 ; VI-LABEL: @select_sge_3xi16(
2770 ; VI-NEXT: [[TMP1:%.*]] = sext <3 x i16> [[A:%.*]] to <3 x i32>
2771 ; VI-NEXT: [[TMP2:%.*]] = sext <3 x i16> [[B:%.*]] to <3 x i32>
2772 ; VI-NEXT: [[TMP3:%.*]] = icmp sge <3 x i32> [[TMP1]], [[TMP2]]
2773 ; VI-NEXT: [[TMP4:%.*]] = sext <3 x i16> [[A]] to <3 x i32>
2774 ; VI-NEXT: [[TMP5:%.*]] = sext <3 x i16> [[B]] to <3 x i32>
2775 ; VI-NEXT: [[TMP6:%.*]] = select <3 x i1> [[TMP3]], <3 x i32> [[TMP4]], <3 x i32> [[TMP5]]
2776 ; VI-NEXT: [[TMP7:%.*]] = trunc <3 x i32> [[TMP6]] to <3 x i16>
2777 ; VI-NEXT: store volatile <3 x i16> [[TMP7]], <3 x i16> addrspace(1)* undef
2778 ; VI-NEXT: ret void
2793 ; VI-LABEL: @select_slt_3xi16(
2794 ; VI-NEXT: [[TMP1:%.*]] = sext <3 x i16> [[A:%.*]] to <3 x i32>
2795 ; VI-NEXT: [[TMP2:%.*]] = sext <3 x i16> [[B:%.*]] to <3 x i32>
2796 ; VI-NEXT: [[TMP3:%.*]] = icmp slt <3 x i32> [[TMP1]], [[TMP2]]
2797 ; VI-NEXT: [[TMP4:%.*]] = sext <3 x i16> [[A]] to <3 x i32>
2798 ; VI-NEXT: [[TMP5:%.*]] = sext <3 x i16> [[B]] to <3 x i32>
2799 ; VI-NEXT: [[TMP6:%.*]] = select <3 x i1> [[TMP3]], <3 x i32> [[TMP4]], <3 x i32> [[TMP5]]
2800 ; VI-NEXT: [[TMP7:%.*]] = trunc <3 x i32> [[TMP6]] to <3 x i16>
2801 ; VI-NEXT: store volatile <3 x i16> [[TMP7]], <3 x i16> addrspace(1)* undef
2802 ; VI-NEXT: ret void
2817 ; VI-LABEL: @select_sle_3xi16(
2818 ; VI-NEXT: [[TMP1:%.*]] = sext <3 x i16> [[A:%.*]] to <3 x i32>
2819 ; VI-NEXT: [[TMP2:%.*]] = sext <3 x i16> [[B:%.*]] to <3 x i32>
2820 ; VI-NEXT: [[TMP3:%.*]] = icmp sle <3 x i32> [[TMP1]], [[TMP2]]
2821 ; VI-NEXT: [[TMP4:%.*]] = sext <3 x i16> [[A]] to <3 x i32>
2822 ; VI-NEXT: [[TMP5:%.*]] = sext <3 x i16> [[B]] to <3 x i32>
2823 ; VI-NEXT: [[TMP6:%.*]] = select <3 x i1> [[TMP3]], <3 x i32> [[TMP4]], <3 x i32> [[TMP5]]
2824 ; VI-NEXT: [[TMP7:%.*]] = trunc <3 x i32> [[TMP6]] to <3 x i16>
2825 ; VI-NEXT: store volatile <3 x i16> [[TMP7]], <3 x i16> addrspace(1)* undef
2826 ; VI-NEXT: ret void
2842 ; VI-LABEL: @bitreverse_3xi16(
2843 ; VI-NEXT: [[TMP1:%.*]] = zext <3 x i16> [[A:%.*]] to <3 x i32>
2844 ; VI-NEXT: [[TMP2:%.*]] = call <3 x i32> @llvm.bitreverse.v3i32(<3 x i32> [[TMP1]])
2845 ; VI-NEXT: [[TMP3:%.*]] = lshr <3 x i32> [[TMP2]], <i32 16, i32 16, i32 16>
2846 ; VI-NEXT: [[TMP4:%.*]] = trunc <3 x i32> [[TMP3]] to <3 x i16>
2847 ; VI-NEXT: store volatile <3 x i16> [[TMP4]], <3 x i16> addrspace(1)* undef
2848 ; VI-NEXT: ret void