Lines Matching refs:MUL
11 ; SI-NEXT: [[MUL:%.*]] = trunc i32 [[TMP3]] to i16
12 ; SI-NEXT: ret i16 [[MUL]]
15 ; VI-NEXT: [[MUL:%.*]] = mul i16 [[LHS:%.*]], [[RHS:%.*]]
16 ; VI-NEXT: ret i16 [[MUL]]
19 ; DISABLED-NEXT: [[MUL:%.*]] = mul i16 [[LHS:%.*]], [[RHS:%.*]]
20 ; DISABLED-NEXT: ret i16 [[MUL]]
32 ; SI-NEXT: [[MUL:%.*]] = call i32 @llvm.amdgcn.mul.i24(i32 [[LHS24]], i32 [[RHS24]])
33 ; SI-NEXT: ret i32 [[MUL]]
40 ; VI-NEXT: [[MUL:%.*]] = call i32 @llvm.amdgcn.mul.i24(i32 [[LHS24]], i32 [[RHS24]])
41 ; VI-NEXT: ret i32 [[MUL]]
48 ; DISABLED-NEXT: [[MUL:%.*]] = mul i32 [[LHS24]], [[RHS24]]
49 ; DISABLED-NEXT: ret i32 [[MUL]]
72 ; SI-NEXT: [[MUL:%.*]] = insertelement <2 x i32> [[TMP7]], i32 [[TMP6]], i64 1
73 ; SI-NEXT: ret <2 x i32> [[MUL]]
87 ; VI-NEXT: [[MUL:%.*]] = insertelement <2 x i32> [[TMP7]], i32 [[TMP6]], i64 1
88 ; VI-NEXT: ret <2 x i32> [[MUL]]
95 ; DISABLED-NEXT: [[MUL:%.*]] = mul <2 x i32> [[LHS24]], [[RHS24]]
96 ; DISABLED-NEXT: ret <2 x i32> [[MUL]]
110 ; SI-NEXT: [[MUL:%.*]] = call i32 @llvm.amdgcn.mul.u24(i32 [[LHS24]], i32 [[RHS24]])
111 ; SI-NEXT: ret i32 [[MUL]]
116 ; VI-NEXT: [[MUL:%.*]] = call i32 @llvm.amdgcn.mul.u24(i32 [[LHS24]], i32 [[RHS24]])
117 ; VI-NEXT: ret i32 [[MUL]]
122 ; DISABLED-NEXT: [[MUL:%.*]] = mul i32 [[LHS24]], [[RHS24]]
123 ; DISABLED-NEXT: ret i32 [[MUL]]
142 ; SI-NEXT: [[MUL:%.*]] = insertelement <2 x i32> [[TMP7]], i32 [[TMP6]], i64 1
143 ; SI-NEXT: ret <2 x i32> [[MUL]]
155 ; VI-NEXT: [[MUL:%.*]] = insertelement <2 x i32> [[TMP7]], i32 [[TMP6]], i64 1
156 ; VI-NEXT: ret <2 x i32> [[MUL]]
161 ; DISABLED-NEXT: [[MUL:%.*]] = mul <2 x i32> [[LHS24]], [[RHS24]]
162 ; DISABLED-NEXT: ret <2 x i32> [[MUL]]
179 ; SI-NEXT: [[MUL:%.*]] = sext i32 [[TMP3]] to i64
180 ; SI-NEXT: ret i64 [[MUL]]
190 ; VI-NEXT: [[MUL:%.*]] = sext i32 [[TMP3]] to i64
191 ; VI-NEXT: ret i64 [[MUL]]
198 ; DISABLED-NEXT: [[MUL:%.*]] = mul i64 [[LHS24]], [[RHS24]]
199 ; DISABLED-NEXT: ret i64 [[MUL]]
216 ; SI-NEXT: [[MUL:%.*]] = zext i32 [[TMP3]] to i64
217 ; SI-NEXT: ret i64 [[MUL]]
225 ; VI-NEXT: [[MUL:%.*]] = zext i32 [[TMP3]] to i64
226 ; VI-NEXT: ret i64 [[MUL]]
231 ; DISABLED-NEXT: [[MUL:%.*]] = mul i64 [[LHS24]], [[RHS24]]
232 ; DISABLED-NEXT: ret i64 [[MUL]]
249 ; SI-NEXT: [[MUL:%.*]] = trunc i32 [[TMP3]] to i31
250 ; SI-NEXT: ret i31 [[MUL]]
260 ; VI-NEXT: [[MUL:%.*]] = trunc i32 [[TMP3]] to i31
261 ; VI-NEXT: ret i31 [[MUL]]
268 ; DISABLED-NEXT: [[MUL:%.*]] = mul i31 [[LHS24]], [[RHS24]]
269 ; DISABLED-NEXT: ret i31 [[MUL]]
286 ; SI-NEXT: [[MUL:%.*]] = trunc i32 [[TMP3]] to i31
287 ; SI-NEXT: ret i31 [[MUL]]
295 ; VI-NEXT: [[MUL:%.*]] = trunc i32 [[TMP3]] to i31
296 ; VI-NEXT: ret i31 [[MUL]]
301 ; DISABLED-NEXT: [[MUL:%.*]] = mul i31 [[LHS24]], [[RHS24]]
302 ; DISABLED-NEXT: ret i31 [[MUL]]
327 ; SI-NEXT: [[MUL:%.*]] = insertelement <2 x i31> [[TMP13]], i31 [[TMP12]], i64 1
328 ; SI-NEXT: ret <2 x i31> [[MUL]]
346 ; VI-NEXT: [[MUL:%.*]] = insertelement <2 x i31> [[TMP13]], i31 [[TMP12]], i64 1
347 ; VI-NEXT: ret <2 x i31> [[MUL]]
352 ; DISABLED-NEXT: [[MUL:%.*]] = mul <2 x i31> [[LHS24]], [[RHS24]]
353 ; DISABLED-NEXT: ret <2 x i31> [[MUL]]
380 ; SI-NEXT: [[MUL:%.*]] = insertelement <2 x i31> [[TMP13]], i31 [[TMP12]], i64 1
381 ; SI-NEXT: ret <2 x i31> [[MUL]]
401 ; VI-NEXT: [[MUL:%.*]] = insertelement <2 x i31> [[TMP13]], i31 [[TMP12]], i64 1
402 ; VI-NEXT: ret <2 x i31> [[MUL]]
409 ; DISABLED-NEXT: [[MUL:%.*]] = mul <2 x i31> [[LHS24]], [[RHS24]]
410 ; DISABLED-NEXT: ret <2 x i31> [[MUL]]
429 ; SI-NEXT: [[MUL:%.*]] = sext i32 [[TMP3]] to i33
430 ; SI-NEXT: ret i33 [[MUL]]
440 ; VI-NEXT: [[MUL:%.*]] = sext i32 [[TMP3]] to i33
441 ; VI-NEXT: ret i33 [[MUL]]
448 ; DISABLED-NEXT: [[MUL:%.*]] = mul i33 [[LHS24]], [[RHS24]]
449 ; DISABLED-NEXT: ret i33 [[MUL]]
466 ; SI-NEXT: [[MUL:%.*]] = zext i32 [[TMP3]] to i33
467 ; SI-NEXT: ret i33 [[MUL]]
475 ; VI-NEXT: [[MUL:%.*]] = zext i32 [[TMP3]] to i33
476 ; VI-NEXT: ret i33 [[MUL]]
481 ; DISABLED-NEXT: [[MUL:%.*]] = mul i33 [[LHS24]], [[RHS24]]
482 ; DISABLED-NEXT: ret i33 [[MUL]]
496 ; SI-NEXT: [[MUL:%.*]] = mul i32 [[LHS24]], [[RHS24]]
497 ; SI-NEXT: ret i32 [[MUL]]
504 ; VI-NEXT: [[MUL:%.*]] = mul i32 [[LHS24]], [[RHS24]]
505 ; VI-NEXT: ret i32 [[MUL]]
512 ; DISABLED-NEXT: [[MUL:%.*]] = mul i32 [[LHS24]], [[RHS24]]
513 ; DISABLED-NEXT: ret i32 [[MUL]]
527 ; SI-NEXT: [[MUL:%.*]] = mul i32 [[LHS24]], [[RHS24]]
528 ; SI-NEXT: ret i32 [[MUL]]
533 ; VI-NEXT: [[MUL:%.*]] = mul i32 [[LHS24]], [[RHS24]]
534 ; VI-NEXT: ret i32 [[MUL]]
539 ; DISABLED-NEXT: [[MUL:%.*]] = mul i32 [[LHS24]], [[RHS24]]
540 ; DISABLED-NEXT: ret i32 [[MUL]]
567 ; SI-NEXT: [[MUL:%.*]] = insertelement <2 x i33> [[TMP13]], i33 [[TMP12]], i64 1
568 ; SI-NEXT: ret <2 x i33> [[MUL]]
588 ; VI-NEXT: [[MUL:%.*]] = insertelement <2 x i33> [[TMP13]], i33 [[TMP12]], i64 1
589 ; VI-NEXT: ret <2 x i33> [[MUL]]
596 ; DISABLED-NEXT: [[MUL:%.*]] = mul <2 x i33> [[LHS24]], [[RHS24]]
597 ; DISABLED-NEXT: ret <2 x i33> [[MUL]]