Lines Matching refs:PAL

9 …verify-machineinstrs < %s | FileCheck --check-prefixes=GCN,GFX9,GFX9_10,FLATSCR,GFX9-FLATSCR-PAL %s
10 … %s | FileCheck --check-prefixes=GCN,GFX10_W32,GFX9_10,FLATSCR,GFX10-FLATSCR-PAL,GFX9_10-FLATSCR %s
30 ; GFX9-FLATSCR-PAL-DAG: s_getpc_b64 s[2:3]
31 ; GFX9-FLATSCR-PAL-DAG: s_mov_b32 s2, s0
32 ; GFX9-FLATSCR-PAL-DAG: s_load_dwordx2 s[2:3], s[2:3], 0x0
33 ; GFX9-FLATSCR-PAL-DAG: v_lshlrev_b32_e32 v0, 2, v0
34 ; GFX9-FLATSCR-PAL-DAG: v_mov_b32_e32 v0, 0xbf20e7f4
35 ; GFX9-FLATSCR-PAL-DAG: s_mov_b32 vcc_hi, 0
36 ; GFX9-FLATSCR-PAL-DAG: s_waitcnt lgkmcnt(0)
37 ; GFX9-FLATSCR-PAL-DAG: s_and_b32 s3, s3, 0xffff
38 ; GFX9-FLATSCR-PAL-DAG: s_add_u32 flat_scratch_lo, s2, s0
39 ; GFX9-FLATSCR-PAL-DAG: s_addc_u32 flat_scratch_hi, s3, 0
40 ; GFX9-FLATSCR-PAL-DAG: v_and_b32_e32 [[CLAMP_IDX:v[0-9]+]], 0x1fc, v0
42 ; GFX10-FLATSCR-PAL: s_getpc_b64 s[2:3]
43 ; GFX10-FLATSCR-PAL: s_mov_b32 s2, s0
44 ; GFX10-FLATSCR-PAL: s_load_dwordx2 s[2:3], s[2:3], 0x0
45 ; GFX10-FLATSCR-PAL: s_waitcnt lgkmcnt(0)
46 ; GFX10-FLATSCR-PAL: s_and_b32 s3, s3, 0xffff
47 ; GFX10-FLATSCR-PAL: s_add_u32 s2, s2, s0
48 ; GFX10-FLATSCR-PAL: s_addc_u32 s3, s3, 0
49 ; GFX10-FLATSCR-PAL: s_setreg_b32 hwreg(HW_REG_FLAT_SCR_LO), s2
50 ; GFX10-FLATSCR-PAL: s_setreg_b32 hwreg(HW_REG_FLAT_SCR_HI), s3
71 ; GFX10-FLATSCR-PAL: v_and_b32_e32 [[CLAMP_IDX:v[0-9]+]], 0x1fc, v0
96 ; GFX9-FLATSCR-PAL-DAG: s_getpc_b64 s[2:3]
97 ; GFX9-FLATSCR-PAL-DAG: s_mov_b32 s2, s0
98 ; GFX9-FLATSCR-PAL-DAG: s_load_dwordx2 s[2:3], s[2:3], 0x0
99 ; GFX9-FLATSCR-PAL-DAG: v_lshlrev_b32_e32 v0, 2, v0
100 ; GFX9-FLATSCR-PAL-DAG: v_mov_b32_e32 v0, 0xbf20e7f4
101 ; GFX9-FLATSCR-PAL-DAG: s_mov_b32 vcc_hi, 0
102 ; GFX9-FLATSCR-PAL-DAG: s_waitcnt lgkmcnt(0)
103 ; GFX9-FLATSCR-PAL-DAG: s_and_b32 s3, s3, 0xffff
104 ; GFX9-FLATSCR-PAL-DAG: s_add_u32 flat_scratch_lo, s2, s0
105 ; GFX9-FLATSCR-PAL-DAG: s_addc_u32 flat_scratch_hi, s3, 0
107 ; GFX10-FLATSCR-PAL: s_getpc_b64 s[2:3]
108 ; GFX10-FLATSCR-PAL: s_mov_b32 s2, s0
109 ; GFX10-FLATSCR-PAL: s_load_dwordx2 s[2:3], s[2:3], 0x0
110 ; GFX10-FLATSCR-PAL: s_waitcnt lgkmcnt(0)
111 ; GFX10-FLATSCR-PAL: s_and_b32 s3, s3, 0xffff
112 ; GFX10-FLATSCR-PAL: s_add_u32 s2, s2, s0
113 ; GFX10-FLATSCR-PAL: s_addc_u32 s3, s3, 0
114 ; GFX10-FLATSCR-PAL: s_setreg_b32 hwreg(HW_REG_FLAT_SCR_LO), s2
115 ; GFX10-FLATSCR-PAL: s_setreg_b32 hwreg(HW_REG_FLAT_SCR_HI), s3
147 ; GFX9-FLATSCR-PAL-DAG: s_getpc_b64 s[2:3]
148 ; GFX9-FLATSCR-PAL-DAG: s_mov_b32 s2, s0
149 ; GFX9-FLATSCR-PAL-DAG: s_load_dwordx2 s[2:3], s[2:3], 0x10
150 ; GFX9-FLATSCR-PAL-DAG: v_lshlrev_b32_e32 v0, 2, v0
151 ; GFX9-FLATSCR-PAL-DAG: v_mov_b32_e32 v0, 0xbf20e7f4
152 ; GFX9-FLATSCR-PAL-DAG: s_mov_b32 vcc_hi, 0
153 ; GFX9-FLATSCR-PAL-DAG: s_waitcnt lgkmcnt(0)
154 ; GFX9-FLATSCR-PAL-DAG: s_and_b32 s3, s3, 0xffff
155 ; GFX9-FLATSCR-PAL-DAG: s_add_u32 flat_scratch_lo, s2, s0
156 ; GFX9-FLATSCR-PAL-DAG: s_addc_u32 flat_scratch_hi, s3, 0
158 ; GFX10-FLATSCR-PAL: s_getpc_b64 s[2:3]
159 ; GFX10-FLATSCR-PAL: s_mov_b32 s2, s0
160 ; GFX10-FLATSCR-PAL: s_load_dwordx2 s[2:3], s[2:3], 0x10
161 ; GFX10-FLATSCR-PAL: s_waitcnt lgkmcnt(0)
162 ; GFX10-FLATSCR-PAL: s_and_b32 s3, s3, 0xffff
163 ; GFX10-FLATSCR-PAL: s_add_u32 s2, s2, s0
164 ; GFX10-FLATSCR-PAL: s_addc_u32 s3, s3, 0
165 ; GFX10-FLATSCR-PAL: s_setreg_b32 hwreg(HW_REG_FLAT_SCR_LO), s2
166 ; GFX10-FLATSCR-PAL: s_setreg_b32 hwreg(HW_REG_FLAT_SCR_HI), s3
222 ; GFX9-FLATSCR-PAL-DAG: s_getpc_b64 s[0:1]
223 ; GFX9-FLATSCR-PAL-DAG: s_mov_b32 s0, s8
224 ; GFX9-FLATSCR-PAL-DAG: s_load_dwordx2 s[0:1], s[0:1], 0x0
225 ; GFX9-FLATSCR-PAL-DAG: v_lshlrev_b32_e32 v0, 2, v0
226 ; GFX9-FLATSCR-PAL-DAG: v_mov_b32_e32 v0, 0xbf20e7f4
227 ; GFX9-FLATSCR-PAL-DAG: s_mov_b32 vcc_hi, 0
228 ; GFX9-FLATSCR-PAL-DAG: s_waitcnt lgkmcnt(0)
229 ; GFX9-FLATSCR-PAL-DAG: s_and_b32 s1, s1, 0xffff
230 ; GFX9-FLATSCR-PAL-DAG: s_add_u32 flat_scratch_lo, s0, s5
231 ; GFX9-FLATSCR-PAL-DAG: s_addc_u32 flat_scratch_hi, s1, 0
233 ; GFX10-FLATSCR-PAL: s_getpc_b64 s[0:1]
234 ; GFX10-FLATSCR-PAL: s_mov_b32 s0, s8
235 ; GFX10-FLATSCR-PAL: s_load_dwordx2 s[0:1], s[0:1], 0x0
236 ; GFX10-FLATSCR-PAL: s_waitcnt lgkmcnt(0)
237 ; GFX10-FLATSCR-PAL: s_and_b32 s1, s1, 0xffff
238 ; GFX10-FLATSCR-PAL: s_add_u32 s0, s0, s5
239 ; GFX10-FLATSCR-PAL: s_addc_u32 s1, s1, 0
240 ; GFX10-FLATSCR-PAL: s_setreg_b32 hwreg(HW_REG_FLAT_SCR_LO), s0
241 ; GFX10-FLATSCR-PAL: s_setreg_b32 hwreg(HW_REG_FLAT_SCR_HI), s1
275 ; GFX9-FLATSCR-PAL-DAG: s_getpc_b64 s[0:1]
276 ; GFX9-FLATSCR-PAL-DAG: s_mov_b32 s0, s8
277 ; GFX9-FLATSCR-PAL-DAG: s_load_dwordx2 s[0:1], s[0:1], 0x0
278 ; GFX9-FLATSCR-PAL-DAG: v_lshlrev_b32_e32 v0, 2, v0
279 ; GFX9-FLATSCR-PAL-DAG: v_mov_b32_e32 v0, 0xbf20e7f4
280 ; GFX9-FLATSCR-PAL-DAG: s_mov_b32 vcc_hi, 0
281 ; GFX9-FLATSCR-PAL-DAG: s_waitcnt lgkmcnt(0)
282 ; GFX9-FLATSCR-PAL-DAG: s_and_b32 s1, s1, 0xffff
283 ; GFX9-FLATSCR-PAL-DAG: s_add_u32 flat_scratch_lo, s0, s5
284 ; GFX9-FLATSCR-PAL-DAG: s_addc_u32 flat_scratch_hi, s1, 0
286 ; GFX10-FLATSCR-PAL: s_getpc_b64 s[0:1]
287 ; GFX10-FLATSCR-PAL: s_mov_b32 s0, s8
288 ; GFX10-FLATSCR-PAL: s_load_dwordx2 s[0:1], s[0:1], 0x0
289 ; GFX10-FLATSCR-PAL: s_waitcnt lgkmcnt(0)
290 ; GFX10-FLATSCR-PAL: s_and_b32 s1, s1, 0xffff
291 ; GFX10-FLATSCR-PAL: s_add_u32 s0, s0, s5
292 ; GFX10-FLATSCR-PAL: s_addc_u32 s1, s1, 0
293 ; GFX10-FLATSCR-PAL: s_setreg_b32 hwreg(HW_REG_FLAT_SCR_LO), s0
294 ; GFX10-FLATSCR-PAL: s_setreg_b32 hwreg(HW_REG_FLAT_SCR_HI), s1
329 ; GFX9-FLATSCR-PAL-DAG: s_getpc_b64 s[0:1]
330 ; GFX9-FLATSCR-PAL-DAG: s_mov_b32 s0, s8
331 ; GFX9-FLATSCR-PAL-DAG: s_load_dwordx2 s[0:1], s[0:1], 0x0
332 ; GFX9-FLATSCR-PAL-DAG: v_lshlrev_b32_e32 v0, 2, v0
333 ; GFX9-FLATSCR-PAL-DAG: v_mov_b32_e32 v0, 0xbf20e7f4
334 ; GFX9-FLATSCR-PAL-DAG: s_mov_b32 vcc_hi, 0
335 ; GFX9-FLATSCR-PAL-DAG: s_waitcnt lgkmcnt(0)
336 ; GFX9-FLATSCR-PAL-DAG: s_and_b32 s1, s1, 0xffff
337 ; GFX9-FLATSCR-PAL-DAG: s_add_u32 flat_scratch_lo, s0, s5
338 ; GFX9-FLATSCR-PAL-DAG: s_addc_u32 flat_scratch_hi, s1, 0
340 ; GFX10-FLATSCR-PAL: s_getpc_b64 s[0:1]
341 ; GFX10-FLATSCR-PAL: s_mov_b32 s0, s8
342 ; GFX10-FLATSCR-PAL: s_load_dwordx2 s[0:1], s[0:1], 0x0
343 ; GFX10-FLATSCR-PAL: s_waitcnt lgkmcnt(0)
344 ; GFX10-FLATSCR-PAL: s_and_b32 s1, s1, 0xffff
345 ; GFX10-FLATSCR-PAL: s_add_u32 s0, s0, s5
346 ; GFX10-FLATSCR-PAL: s_addc_u32 s1, s1, 0
347 ; GFX10-FLATSCR-PAL: s_setreg_b32 hwreg(HW_REG_FLAT_SCR_LO), s0
348 ; GFX10-FLATSCR-PAL: s_setreg_b32 hwreg(HW_REG_FLAT_SCR_HI), s1