Lines Matching refs:IR
3 … -amdgpu-codegenprepare-expand-div64 -verify-machineinstrs < %s | FileCheck -check-prefix=GCN-IR %s
127 ; GCN-IR-LABEL: s_test_srem:
128 ; GCN-IR: ; %bb.0: ; %_udiv-special-cases
129 ; GCN-IR-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x9
130 ; GCN-IR-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0xd
131 ; GCN-IR-NEXT: s_waitcnt lgkmcnt(0)
132 ; GCN-IR-NEXT: v_cmp_eq_u64_e64 s[8:9], s[6:7], 0
133 ; GCN-IR-NEXT: s_flbit_i32_b32 s10, s2
134 ; GCN-IR-NEXT: s_add_i32 s10, s10, 32
135 ; GCN-IR-NEXT: s_flbit_i32_b32 s11, s3
136 ; GCN-IR-NEXT: v_mov_b32_e32 v1, s10
137 ; GCN-IR-NEXT: s_flbit_i32_b32 s10, s6
138 ; GCN-IR-NEXT: v_mov_b32_e32 v0, s11
139 ; GCN-IR-NEXT: v_cmp_eq_u32_e64 vcc, s3, 0
140 ; GCN-IR-NEXT: s_add_i32 s10, s10, 32
141 ; GCN-IR-NEXT: s_flbit_i32_b32 s11, s7
142 ; GCN-IR-NEXT: v_cndmask_b32_e32 v2, v0, v1, vcc
143 ; GCN-IR-NEXT: v_mov_b32_e32 v0, s11
144 ; GCN-IR-NEXT: v_mov_b32_e32 v1, s10
145 ; GCN-IR-NEXT: v_cmp_eq_u32_e64 vcc, s7, 0
146 ; GCN-IR-NEXT: v_cndmask_b32_e32 v3, v0, v1, vcc
147 ; GCN-IR-NEXT: v_sub_i32_e32 v0, vcc, v2, v3
148 ; GCN-IR-NEXT: v_cmp_eq_u64_e64 s[0:1], s[2:3], 0
149 ; GCN-IR-NEXT: v_subb_u32_e64 v1, s[10:11], 0, 0, vcc
150 ; GCN-IR-NEXT: v_cmp_lt_u64_e32 vcc, 63, v[0:1]
151 ; GCN-IR-NEXT: s_or_b64 s[0:1], s[0:1], s[8:9]
152 ; GCN-IR-NEXT: s_or_b64 s[0:1], s[0:1], vcc
153 ; GCN-IR-NEXT: v_cmp_ne_u64_e32 vcc, 63, v[0:1]
154 ; GCN-IR-NEXT: s_xor_b64 s[8:9], s[0:1], -1
155 ; GCN-IR-NEXT: s_and_b64 s[8:9], s[8:9], vcc
156 ; GCN-IR-NEXT: s_and_b64 vcc, exec, s[8:9]
157 ; GCN-IR-NEXT: s_cbranch_vccz BB0_4
158 ; GCN-IR-NEXT: ; %bb.1: ; %udiv-bb1
159 ; GCN-IR-NEXT: v_add_i32_e32 v4, vcc, 1, v0
160 ; GCN-IR-NEXT: v_addc_u32_e32 v5, vcc, 0, v1, vcc
161 ; GCN-IR-NEXT: v_cmp_lt_u64_e64 s[0:1], v[4:5], v[0:1]
162 ; GCN-IR-NEXT: v_sub_i32_e32 v0, vcc, 63, v0
163 ; GCN-IR-NEXT: v_lshl_b64 v[0:1], s[6:7], v0
164 ; GCN-IR-NEXT: s_andn2_b64 vcc, exec, s[0:1]
165 ; GCN-IR-NEXT: s_cbranch_vccz BB0_5
166 ; GCN-IR-NEXT: ; %bb.2: ; %udiv-preheader
167 ; GCN-IR-NEXT: v_not_b32_e32 v2, v2
168 ; GCN-IR-NEXT: s_add_u32 s8, s2, -1
169 ; GCN-IR-NEXT: v_lshr_b64 v[6:7], s[6:7], v4
170 ; GCN-IR-NEXT: v_add_i32_e32 v4, vcc, v2, v3
171 ; GCN-IR-NEXT: v_mov_b32_e32 v8, 0
172 ; GCN-IR-NEXT: s_addc_u32 s9, s3, -1
173 ; GCN-IR-NEXT: v_addc_u32_e64 v5, s[0:1], -1, 0, vcc
174 ; GCN-IR-NEXT: v_mov_b32_e32 v9, 0
175 ; GCN-IR-NEXT: v_mov_b32_e32 v3, 0
176 ; GCN-IR-NEXT: BB0_3: ; %udiv-do-while
177 ; GCN-IR-NEXT: ; =>This Inner Loop Header: Depth=1
178 ; GCN-IR-NEXT: v_lshl_b64 v[6:7], v[6:7], 1
179 ; GCN-IR-NEXT: v_lshrrev_b32_e32 v2, 31, v1
180 ; GCN-IR-NEXT: v_lshl_b64 v[0:1], v[0:1], 1
181 ; GCN-IR-NEXT: v_or_b32_e32 v6, v6, v2
182 ; GCN-IR-NEXT: v_or_b32_e32 v0, v8, v0
183 ; GCN-IR-NEXT: v_mov_b32_e32 v2, s9
184 ; GCN-IR-NEXT: v_sub_i32_e32 v8, vcc, s8, v6
185 ; GCN-IR-NEXT: v_subb_u32_e32 v2, vcc, v2, v7, vcc
186 ; GCN-IR-NEXT: v_ashrrev_i32_e32 v8, 31, v2
187 ; GCN-IR-NEXT: v_and_b32_e32 v10, s2, v8
188 ; GCN-IR-NEXT: v_and_b32_e32 v2, 1, v8
189 ; GCN-IR-NEXT: v_and_b32_e32 v11, s3, v8
190 ; GCN-IR-NEXT: v_add_i32_e32 v8, vcc, 1, v4
191 ; GCN-IR-NEXT: v_or_b32_e32 v1, v9, v1
192 ; GCN-IR-NEXT: v_addc_u32_e32 v9, vcc, 0, v5, vcc
193 ; GCN-IR-NEXT: v_cmp_lt_u64_e32 vcc, v[8:9], v[4:5]
194 ; GCN-IR-NEXT: v_mov_b32_e32 v4, v8
195 ; GCN-IR-NEXT: v_sub_i32_e64 v6, s[0:1], v6, v10
196 ; GCN-IR-NEXT: v_mov_b32_e32 v5, v9
197 ; GCN-IR-NEXT: v_mov_b32_e32 v9, v3
198 ; GCN-IR-NEXT: v_subb_u32_e64 v7, s[0:1], v7, v11, s[0:1]
199 ; GCN-IR-NEXT: s_and_b64 vcc, exec, vcc
200 ; GCN-IR-NEXT: v_mov_b32_e32 v8, v2
201 ; GCN-IR-NEXT: s_cbranch_vccz BB0_3
202 ; GCN-IR-NEXT: s_branch BB0_6
203 ; GCN-IR-NEXT: BB0_4:
204 ; GCN-IR-NEXT: v_mov_b32_e32 v0, s7
205 ; GCN-IR-NEXT: v_cndmask_b32_e64 v1, v0, 0, s[0:1]
206 ; GCN-IR-NEXT: v_mov_b32_e32 v0, s6
207 ; GCN-IR-NEXT: v_cndmask_b32_e64 v0, v0, 0, s[0:1]
208 ; GCN-IR-NEXT: s_branch BB0_7
209 ; GCN-IR-NEXT: BB0_5:
210 ; GCN-IR-NEXT: v_mov_b32_e32 v2, 0
211 ; GCN-IR-NEXT: v_mov_b32_e32 v3, 0
212 ; GCN-IR-NEXT: BB0_6: ; %Flow6
213 ; GCN-IR-NEXT: v_lshl_b64 v[0:1], v[0:1], 1
214 ; GCN-IR-NEXT: v_or_b32_e32 v0, v2, v0
215 ; GCN-IR-NEXT: v_or_b32_e32 v1, v3, v1
216 ; GCN-IR-NEXT: BB0_7: ; %udiv-end
217 ; GCN-IR-NEXT: v_mul_lo_u32 v1, s2, v1
218 ; GCN-IR-NEXT: v_mul_hi_u32 v2, s2, v0
219 ; GCN-IR-NEXT: v_mul_lo_u32 v3, s3, v0
220 ; GCN-IR-NEXT: v_mul_lo_u32 v0, s2, v0
221 ; GCN-IR-NEXT: s_mov_b32 s11, 0xf000
222 ; GCN-IR-NEXT: v_add_i32_e32 v1, vcc, v2, v1
223 ; GCN-IR-NEXT: v_add_i32_e32 v1, vcc, v1, v3
224 ; GCN-IR-NEXT: v_mov_b32_e32 v2, s7
225 ; GCN-IR-NEXT: v_sub_i32_e32 v0, vcc, s6, v0
226 ; GCN-IR-NEXT: s_mov_b32 s10, -1
227 ; GCN-IR-NEXT: s_mov_b32 s8, s4
228 ; GCN-IR-NEXT: s_mov_b32 s9, s5
229 ; GCN-IR-NEXT: v_subb_u32_e32 v1, vcc, v2, v1, vcc
230 ; GCN-IR-NEXT: buffer_store_dwordx2 v[0:1], off, s[8:11], 0
231 ; GCN-IR-NEXT: s_endpgm
364 ; GCN-IR-LABEL: v_test_srem:
365 ; GCN-IR: ; %bb.0: ; %_udiv-special-cases
366 ; GCN-IR-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
367 ; GCN-IR-NEXT: v_ashrrev_i32_e32 v4, 31, v1
368 ; GCN-IR-NEXT: v_xor_b32_e32 v0, v0, v4
369 ; GCN-IR-NEXT: v_ashrrev_i32_e32 v6, 31, v3
370 ; GCN-IR-NEXT: v_xor_b32_e32 v1, v1, v4
371 ; GCN-IR-NEXT: v_sub_i32_e32 v0, vcc, v0, v4
372 ; GCN-IR-NEXT: v_subb_u32_e32 v1, vcc, v1, v4, vcc
373 ; GCN-IR-NEXT: v_xor_b32_e32 v2, v2, v6
374 ; GCN-IR-NEXT: v_sub_i32_e32 v5, vcc, v2, v6
375 ; GCN-IR-NEXT: v_xor_b32_e32 v3, v3, v6
376 ; GCN-IR-NEXT: v_subb_u32_e32 v6, vcc, v3, v6, vcc
377 ; GCN-IR-NEXT: v_cmp_eq_u64_e32 vcc, 0, v[5:6]
378 ; GCN-IR-NEXT: v_cmp_eq_u64_e64 s[4:5], 0, v[0:1]
379 ; GCN-IR-NEXT: v_ffbh_u32_e32 v3, v5
380 ; GCN-IR-NEXT: s_or_b64 s[6:7], vcc, s[4:5]
381 ; GCN-IR-NEXT: v_add_i32_e32 v3, vcc, 32, v3
382 ; GCN-IR-NEXT: v_ffbh_u32_e32 v7, v6
383 ; GCN-IR-NEXT: v_cmp_eq_u32_e32 vcc, 0, v6
384 ; GCN-IR-NEXT: v_cndmask_b32_e32 v12, v7, v3, vcc
385 ; GCN-IR-NEXT: v_ffbh_u32_e32 v3, v0
386 ; GCN-IR-NEXT: v_add_i32_e32 v3, vcc, 32, v3
387 ; GCN-IR-NEXT: v_ffbh_u32_e32 v7, v1
388 ; GCN-IR-NEXT: v_cmp_eq_u32_e32 vcc, 0, v1
389 ; GCN-IR-NEXT: v_cndmask_b32_e32 v14, v7, v3, vcc
390 ; GCN-IR-NEXT: v_sub_i32_e32 v7, vcc, v12, v14
391 ; GCN-IR-NEXT: v_subb_u32_e64 v8, s[4:5], 0, 0, vcc
392 ; GCN-IR-NEXT: v_cmp_lt_u64_e32 vcc, 63, v[7:8]
393 ; GCN-IR-NEXT: v_cmp_ne_u64_e64 s[4:5], 63, v[7:8]
394 ; GCN-IR-NEXT: s_or_b64 s[6:7], s[6:7], vcc
395 ; GCN-IR-NEXT: v_mov_b32_e32 v13, 0
396 ; GCN-IR-NEXT: s_xor_b64 s[8:9], s[6:7], -1
397 ; GCN-IR-NEXT: v_mov_b32_e32 v2, v4
398 ; GCN-IR-NEXT: v_mov_b32_e32 v15, v13
399 ; GCN-IR-NEXT: v_cndmask_b32_e64 v3, v1, 0, s[6:7]
400 ; GCN-IR-NEXT: s_and_b64 s[4:5], s[8:9], s[4:5]
401 ; GCN-IR-NEXT: v_cndmask_b32_e64 v9, v0, 0, s[6:7]
402 ; GCN-IR-NEXT: s_and_saveexec_b64 s[6:7], s[4:5]
403 ; GCN-IR-NEXT: s_cbranch_execz BB1_6
404 ; GCN-IR-NEXT: ; %bb.1: ; %udiv-bb1
405 ; GCN-IR-NEXT: v_add_i32_e32 v9, vcc, 1, v7
406 ; GCN-IR-NEXT: v_addc_u32_e32 v10, vcc, 0, v8, vcc
407 ; GCN-IR-NEXT: v_sub_i32_e64 v3, s[4:5], 63, v7
408 ; GCN-IR-NEXT: v_cmp_ge_u64_e32 vcc, v[9:10], v[7:8]
409 ; GCN-IR-NEXT: v_mov_b32_e32 v10, 0
410 ; GCN-IR-NEXT: v_lshl_b64 v[7:8], v[0:1], v3
411 ; GCN-IR-NEXT: s_mov_b64 s[8:9], 0
412 ; GCN-IR-NEXT: v_mov_b32_e32 v11, 0
413 ; GCN-IR-NEXT: s_and_saveexec_b64 s[4:5], vcc
414 ; GCN-IR-NEXT: s_xor_b64 s[10:11], exec, s[4:5]
415 ; GCN-IR-NEXT: s_cbranch_execz BB1_5
416 ; GCN-IR-NEXT: ; %bb.2: ; %udiv-preheader
417 ; GCN-IR-NEXT: v_add_i32_e32 v3, vcc, -1, v5
418 ; GCN-IR-NEXT: v_lshr_b64 v[16:17], v[0:1], v9
419 ; GCN-IR-NEXT: v_addc_u32_e32 v9, vcc, -1, v6, vcc
420 ; GCN-IR-NEXT: v_not_b32_e32 v10, v12
421 ; GCN-IR-NEXT: v_not_b32_e32 v11, v13
422 ; GCN-IR-NEXT: v_add_i32_e32 v12, vcc, v10, v14
423 ; GCN-IR-NEXT: v_addc_u32_e32 v13, vcc, v11, v15, vcc
424 ; GCN-IR-NEXT: v_mov_b32_e32 v14, 0
425 ; GCN-IR-NEXT: v_mov_b32_e32 v15, 0
426 ; GCN-IR-NEXT: BB1_3: ; %udiv-do-while
427 ; GCN-IR-NEXT: ; =>This Inner Loop Header: Depth=1
428 ; GCN-IR-NEXT: v_lshl_b64 v[16:17], v[16:17], 1
429 ; GCN-IR-NEXT: v_lshrrev_b32_e32 v10, 31, v8
430 ; GCN-IR-NEXT: v_or_b32_e32 v16, v16, v10
431 ; GCN-IR-NEXT: v_lshl_b64 v[7:8], v[7:8], 1
432 ; GCN-IR-NEXT: v_sub_i32_e32 v10, vcc, v3, v16
433 ; GCN-IR-NEXT: v_subb_u32_e32 v10, vcc, v9, v17, vcc
434 ; GCN-IR-NEXT: v_or_b32_e32 v7, v14, v7
435 ; GCN-IR-NEXT: v_ashrrev_i32_e32 v14, 31, v10
436 ; GCN-IR-NEXT: v_and_b32_e32 v19, v14, v5
437 ; GCN-IR-NEXT: v_and_b32_e32 v10, 1, v14
438 ; GCN-IR-NEXT: v_and_b32_e32 v18, v14, v6
439 ; GCN-IR-NEXT: v_add_i32_e32 v14, vcc, 1, v12
440 ; GCN-IR-NEXT: v_or_b32_e32 v8, v15, v8
441 ; GCN-IR-NEXT: v_addc_u32_e32 v15, vcc, 0, v13, vcc
442 ; GCN-IR-NEXT: v_cmp_lt_u64_e32 vcc, v[14:15], v[12:13]
443 ; GCN-IR-NEXT: v_mov_b32_e32 v12, v14
444 ; GCN-IR-NEXT: v_mov_b32_e32 v11, 0
445 ; GCN-IR-NEXT: v_sub_i32_e64 v16, s[4:5], v16, v19
446 ; GCN-IR-NEXT: v_mov_b32_e32 v13, v15
447 ; GCN-IR-NEXT: v_mov_b32_e32 v15, v11
448 ; GCN-IR-NEXT: v_subb_u32_e64 v17, s[4:5], v17, v18, s[4:5]
449 ; GCN-IR-NEXT: s_or_b64 s[8:9], vcc, s[8:9]
450 ; GCN-IR-NEXT: v_mov_b32_e32 v14, v10
451 ; GCN-IR-NEXT: s_andn2_b64 exec, exec, s[8:9]
452 ; GCN-IR-NEXT: s_cbranch_execnz BB1_3
453 ; GCN-IR-NEXT: ; %bb.4: ; %Flow
454 ; GCN-IR-NEXT: s_or_b64 exec, exec, s[8:9]
455 ; GCN-IR-NEXT: BB1_5: ; %Flow3
456 ; GCN-IR-NEXT: s_or_b64 exec, exec, s[10:11]
457 ; GCN-IR-NEXT: v_lshl_b64 v[7:8], v[7:8], 1
458 ; GCN-IR-NEXT: v_or_b32_e32 v3, v11, v8
459 ; GCN-IR-NEXT: v_or_b32_e32 v9, v10, v7
460 ; GCN-IR-NEXT: BB1_6: ; %Flow4
461 ; GCN-IR-NEXT: s_or_b64 exec, exec, s[6:7]
462 ; GCN-IR-NEXT: v_mul_lo_u32 v3, v5, v3
463 ; GCN-IR-NEXT: v_mul_hi_u32 v7, v5, v9
464 ; GCN-IR-NEXT: v_mul_lo_u32 v6, v6, v9
465 ; GCN-IR-NEXT: v_mul_lo_u32 v5, v5, v9
466 ; GCN-IR-NEXT: v_add_i32_e32 v3, vcc, v7, v3
467 ; GCN-IR-NEXT: v_add_i32_e32 v3, vcc, v3, v6
468 ; GCN-IR-NEXT: v_sub_i32_e32 v0, vcc, v0, v5
469 ; GCN-IR-NEXT: v_subb_u32_e32 v1, vcc, v1, v3, vcc
470 ; GCN-IR-NEXT: v_xor_b32_e32 v0, v0, v4
471 ; GCN-IR-NEXT: v_xor_b32_e32 v1, v1, v2
472 ; GCN-IR-NEXT: v_sub_i32_e32 v0, vcc, v0, v4
473 ; GCN-IR-NEXT: v_subb_u32_e32 v1, vcc, v1, v2, vcc
474 ; GCN-IR-NEXT: s_setpc_b64 s[30:31]
512 ; GCN-IR-LABEL: s_test_srem23_64:
513 ; GCN-IR: ; %bb.0:
514 ; GCN-IR-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x9
515 ; GCN-IR-NEXT: s_load_dword s1, s[0:1], 0xe
516 ; GCN-IR-NEXT: s_mov_b32 s3, 0xf000
517 ; GCN-IR-NEXT: s_mov_b32 s2, -1
518 ; GCN-IR-NEXT: s_waitcnt lgkmcnt(0)
519 ; GCN-IR-NEXT: s_ashr_i64 s[6:7], s[6:7], 41
520 ; GCN-IR-NEXT: s_ashr_i64 s[0:1], s[0:1], 41
521 ; GCN-IR-NEXT: v_cvt_f32_i32_e32 v0, s0
522 ; GCN-IR-NEXT: v_cvt_f32_i32_e32 v1, s6
523 ; GCN-IR-NEXT: s_xor_b32 s1, s6, s0
524 ; GCN-IR-NEXT: s_ashr_i32 s1, s1, 30
525 ; GCN-IR-NEXT: v_rcp_iflag_f32_e32 v2, v0
526 ; GCN-IR-NEXT: s_or_b32 s1, s1, 1
527 ; GCN-IR-NEXT: v_mov_b32_e32 v3, s1
528 ; GCN-IR-NEXT: s_mov_b32 s1, s5
529 ; GCN-IR-NEXT: v_mul_f32_e32 v2, v1, v2
530 ; GCN-IR-NEXT: v_trunc_f32_e32 v2, v2
531 ; GCN-IR-NEXT: v_mad_f32 v1, -v2, v0, v1
532 ; GCN-IR-NEXT: v_cvt_i32_f32_e32 v2, v2
533 ; GCN-IR-NEXT: v_cmp_ge_f32_e64 vcc, |v1|, |v0|
534 ; GCN-IR-NEXT: v_cndmask_b32_e32 v0, 0, v3, vcc
535 ; GCN-IR-NEXT: v_add_i32_e32 v0, vcc, v0, v2
536 ; GCN-IR-NEXT: v_mul_lo_u32 v0, v0, s0
537 ; GCN-IR-NEXT: s_mov_b32 s0, s4
538 ; GCN-IR-NEXT: v_sub_i32_e32 v0, vcc, s6, v0
539 ; GCN-IR-NEXT: v_bfe_i32 v0, v0, 0, 23
540 ; GCN-IR-NEXT: v_ashrrev_i32_e32 v1, 31, v0
541 ; GCN-IR-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0
542 ; GCN-IR-NEXT: s_endpgm
583 ; GCN-IR-LABEL: s_test_srem24_64:
584 ; GCN-IR: ; %bb.0:
585 ; GCN-IR-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x9
586 ; GCN-IR-NEXT: s_load_dword s1, s[0:1], 0xe
587 ; GCN-IR-NEXT: s_mov_b32 s3, 0xf000
588 ; GCN-IR-NEXT: s_mov_b32 s2, -1
589 ; GCN-IR-NEXT: s_waitcnt lgkmcnt(0)
590 ; GCN-IR-NEXT: s_ashr_i64 s[6:7], s[6:7], 40
591 ; GCN-IR-NEXT: s_ashr_i64 s[0:1], s[0:1], 40
592 ; GCN-IR-NEXT: v_cvt_f32_i32_e32 v0, s0
593 ; GCN-IR-NEXT: v_cvt_f32_i32_e32 v1, s6
594 ; GCN-IR-NEXT: s_xor_b32 s1, s6, s0
595 ; GCN-IR-NEXT: s_ashr_i32 s1, s1, 30
596 ; GCN-IR-NEXT: v_rcp_iflag_f32_e32 v2, v0
597 ; GCN-IR-NEXT: s_or_b32 s1, s1, 1
598 ; GCN-IR-NEXT: v_mov_b32_e32 v3, s1
599 ; GCN-IR-NEXT: s_mov_b32 s1, s5
600 ; GCN-IR-NEXT: v_mul_f32_e32 v2, v1, v2
601 ; GCN-IR-NEXT: v_trunc_f32_e32 v2, v2
602 ; GCN-IR-NEXT: v_mad_f32 v1, -v2, v0, v1
603 ; GCN-IR-NEXT: v_cvt_i32_f32_e32 v2, v2
604 ; GCN-IR-NEXT: v_cmp_ge_f32_e64 vcc, |v1|, |v0|
605 ; GCN-IR-NEXT: v_cndmask_b32_e32 v0, 0, v3, vcc
606 ; GCN-IR-NEXT: v_add_i32_e32 v0, vcc, v0, v2
607 ; GCN-IR-NEXT: v_mul_lo_u32 v0, v0, s0
608 ; GCN-IR-NEXT: s_mov_b32 s0, s4
609 ; GCN-IR-NEXT: v_sub_i32_e32 v0, vcc, s6, v0
610 ; GCN-IR-NEXT: v_bfe_i32 v0, v0, 0, 24
611 ; GCN-IR-NEXT: v_ashrrev_i32_e32 v1, 31, v0
612 ; GCN-IR-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0
613 ; GCN-IR-NEXT: s_endpgm
646 ; GCN-IR-LABEL: v_test_srem24_64:
647 ; GCN-IR: ; %bb.0:
648 ; GCN-IR-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
649 ; GCN-IR-NEXT: v_ashr_i64 v[2:3], v[2:3], 40
650 ; GCN-IR-NEXT: v_ashr_i64 v[0:1], v[0:1], 40
651 ; GCN-IR-NEXT: v_cvt_f32_i32_e32 v3, v2
652 ; GCN-IR-NEXT: v_cvt_f32_i32_e32 v1, v0
653 ; GCN-IR-NEXT: v_xor_b32_e32 v5, v0, v2
654 ; GCN-IR-NEXT: v_ashrrev_i32_e32 v5, 30, v5
655 ; GCN-IR-NEXT: v_rcp_iflag_f32_e32 v4, v3
656 ; GCN-IR-NEXT: v_or_b32_e32 v5, 1, v5
657 ; GCN-IR-NEXT: v_mul_f32_e32 v4, v1, v4
658 ; GCN-IR-NEXT: v_trunc_f32_e32 v4, v4
659 ; GCN-IR-NEXT: v_mad_f32 v1, -v4, v3, v1
660 ; GCN-IR-NEXT: v_cvt_i32_f32_e32 v4, v4
661 ; GCN-IR-NEXT: v_cmp_ge_f32_e64 vcc, |v1|, |v3|
662 ; GCN-IR-NEXT: v_cndmask_b32_e32 v1, 0, v5, vcc
663 ; GCN-IR-NEXT: v_add_i32_e32 v1, vcc, v4, v1
664 ; GCN-IR-NEXT: v_mul_lo_u32 v1, v1, v2
665 ; GCN-IR-NEXT: v_sub_i32_e32 v0, vcc, v0, v1
666 ; GCN-IR-NEXT: v_bfe_i32 v0, v0, 0, 24
667 ; GCN-IR-NEXT: v_ashrrev_i32_e32 v1, 31, v0
668 ; GCN-IR-NEXT: s_setpc_b64 s[30:31]
708 ; GCN-IR-LABEL: s_test_srem25_64:
709 ; GCN-IR: ; %bb.0:
710 ; GCN-IR-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x9
711 ; GCN-IR-NEXT: s_load_dword s1, s[0:1], 0xe
712 ; GCN-IR-NEXT: s_mov_b32 s3, 0xf000
713 ; GCN-IR-NEXT: s_mov_b32 s2, -1
714 ; GCN-IR-NEXT: s_waitcnt lgkmcnt(0)
715 ; GCN-IR-NEXT: s_ashr_i64 s[6:7], s[6:7], 39
716 ; GCN-IR-NEXT: s_ashr_i64 s[0:1], s[0:1], 39
717 ; GCN-IR-NEXT: v_cvt_f32_i32_e32 v0, s0
718 ; GCN-IR-NEXT: v_cvt_f32_i32_e32 v1, s6
719 ; GCN-IR-NEXT: s_xor_b32 s1, s6, s0
720 ; GCN-IR-NEXT: s_ashr_i32 s1, s1, 30
721 ; GCN-IR-NEXT: v_rcp_iflag_f32_e32 v2, v0
722 ; GCN-IR-NEXT: s_or_b32 s1, s1, 1
723 ; GCN-IR-NEXT: v_mov_b32_e32 v3, s1
724 ; GCN-IR-NEXT: s_mov_b32 s1, s5
725 ; GCN-IR-NEXT: v_mul_f32_e32 v2, v1, v2
726 ; GCN-IR-NEXT: v_trunc_f32_e32 v2, v2
727 ; GCN-IR-NEXT: v_mad_f32 v1, -v2, v0, v1
728 ; GCN-IR-NEXT: v_cvt_i32_f32_e32 v2, v2
729 ; GCN-IR-NEXT: v_cmp_ge_f32_e64 vcc, |v1|, |v0|
730 ; GCN-IR-NEXT: v_cndmask_b32_e32 v0, 0, v3, vcc
731 ; GCN-IR-NEXT: v_add_i32_e32 v0, vcc, v0, v2
732 ; GCN-IR-NEXT: v_mul_lo_u32 v0, v0, s0
733 ; GCN-IR-NEXT: s_mov_b32 s0, s4
734 ; GCN-IR-NEXT: v_sub_i32_e32 v0, vcc, s6, v0
735 ; GCN-IR-NEXT: v_bfe_i32 v0, v0, 0, 25
736 ; GCN-IR-NEXT: v_ashrrev_i32_e32 v1, 31, v0
737 ; GCN-IR-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0
738 ; GCN-IR-NEXT: s_endpgm
779 ; GCN-IR-LABEL: s_test_srem31_64:
780 ; GCN-IR: ; %bb.0:
781 ; GCN-IR-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x9
782 ; GCN-IR-NEXT: s_load_dword s1, s[0:1], 0xe
783 ; GCN-IR-NEXT: s_mov_b32 s3, 0xf000
784 ; GCN-IR-NEXT: s_mov_b32 s2, -1
785 ; GCN-IR-NEXT: s_waitcnt lgkmcnt(0)
786 ; GCN-IR-NEXT: s_ashr_i64 s[6:7], s[6:7], 33
787 ; GCN-IR-NEXT: s_ashr_i64 s[0:1], s[0:1], 33
788 ; GCN-IR-NEXT: v_cvt_f32_i32_e32 v0, s0
789 ; GCN-IR-NEXT: v_cvt_f32_i32_e32 v1, s6
790 ; GCN-IR-NEXT: s_xor_b32 s1, s6, s0
791 ; GCN-IR-NEXT: s_ashr_i32 s1, s1, 30
792 ; GCN-IR-NEXT: v_rcp_iflag_f32_e32 v2, v0
793 ; GCN-IR-NEXT: s_or_b32 s1, s1, 1
794 ; GCN-IR-NEXT: v_mov_b32_e32 v3, s1
795 ; GCN-IR-NEXT: s_mov_b32 s1, s5
796 ; GCN-IR-NEXT: v_mul_f32_e32 v2, v1, v2
797 ; GCN-IR-NEXT: v_trunc_f32_e32 v2, v2
798 ; GCN-IR-NEXT: v_mad_f32 v1, -v2, v0, v1
799 ; GCN-IR-NEXT: v_cvt_i32_f32_e32 v2, v2
800 ; GCN-IR-NEXT: v_cmp_ge_f32_e64 vcc, |v1|, |v0|
801 ; GCN-IR-NEXT: v_cndmask_b32_e32 v0, 0, v3, vcc
802 ; GCN-IR-NEXT: v_add_i32_e32 v0, vcc, v0, v2
803 ; GCN-IR-NEXT: v_mul_lo_u32 v0, v0, s0
804 ; GCN-IR-NEXT: s_mov_b32 s0, s4
805 ; GCN-IR-NEXT: v_sub_i32_e32 v0, vcc, s6, v0
806 ; GCN-IR-NEXT: v_bfe_i32 v0, v0, 0, 31
807 ; GCN-IR-NEXT: v_ashrrev_i32_e32 v1, 31, v0
808 ; GCN-IR-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0
809 ; GCN-IR-NEXT: s_endpgm
848 ; GCN-IR-LABEL: s_test_srem32_64:
849 ; GCN-IR: ; %bb.0:
850 ; GCN-IR-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x9
851 ; GCN-IR-NEXT: s_load_dword s0, s[0:1], 0xe
852 ; GCN-IR-NEXT: s_mov_b32 s3, 0xf000
853 ; GCN-IR-NEXT: s_mov_b32 s2, -1
854 ; GCN-IR-NEXT: s_waitcnt lgkmcnt(0)
855 ; GCN-IR-NEXT: v_cvt_f32_i32_e32 v1, s7
856 ; GCN-IR-NEXT: v_cvt_f32_i32_e32 v0, s0
857 ; GCN-IR-NEXT: s_xor_b32 s1, s7, s0
858 ; GCN-IR-NEXT: s_ashr_i32 s1, s1, 30
859 ; GCN-IR-NEXT: s_or_b32 s1, s1, 1
860 ; GCN-IR-NEXT: v_rcp_iflag_f32_e32 v2, v0
861 ; GCN-IR-NEXT: v_mov_b32_e32 v3, s1
862 ; GCN-IR-NEXT: s_mov_b32 s1, s5
863 ; GCN-IR-NEXT: v_mul_f32_e32 v2, v1, v2
864 ; GCN-IR-NEXT: v_trunc_f32_e32 v2, v2
865 ; GCN-IR-NEXT: v_mad_f32 v1, -v2, v0, v1
866 ; GCN-IR-NEXT: v_cvt_i32_f32_e32 v2, v2
867 ; GCN-IR-NEXT: v_cmp_ge_f32_e64 vcc, |v1|, |v0|
868 ; GCN-IR-NEXT: v_cndmask_b32_e32 v0, 0, v3, vcc
869 ; GCN-IR-NEXT: v_add_i32_e32 v0, vcc, v0, v2
870 ; GCN-IR-NEXT: v_mul_lo_u32 v0, v0, s0
871 ; GCN-IR-NEXT: s_mov_b32 s0, s4
872 ; GCN-IR-NEXT: v_sub_i32_e32 v0, vcc, s7, v0
873 ; GCN-IR-NEXT: v_ashrrev_i32_e32 v1, 31, v0
874 ; GCN-IR-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0
875 ; GCN-IR-NEXT: s_endpgm
1023 ; GCN-IR-LABEL: s_test_srem33_64:
1024 ; GCN-IR: ; %bb.0: ; %_udiv-special-cases
1025 ; GCN-IR-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x9
1026 ; GCN-IR-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0xd
1027 ; GCN-IR-NEXT: s_waitcnt lgkmcnt(0)
1028 ; GCN-IR-NEXT: s_ashr_i32 s2, s7, 31
1029 ; GCN-IR-NEXT: s_ashr_i64 s[10:11], s[0:1], 31
1030 ; GCN-IR-NEXT: s_ashr_i32 s0, s1, 31
1031 ; GCN-IR-NEXT: s_mov_b32 s1, s0
1032 ; GCN-IR-NEXT: s_ashr_i64 s[8:9], s[6:7], 31
1033 ; GCN-IR-NEXT: s_mov_b32 s3, s2
1034 ; GCN-IR-NEXT: s_xor_b64 s[6:7], s[8:9], s[2:3]
1035 ; GCN-IR-NEXT: s_xor_b64 s[10:11], s[10:11], s[0:1]
1036 ; GCN-IR-NEXT: s_sub_u32 s8, s6, s2
1037 ; GCN-IR-NEXT: s_subb_u32 s9, s7, s2
1038 ; GCN-IR-NEXT: s_sub_u32 s10, s10, s0
1039 ; GCN-IR-NEXT: s_flbit_i32_b32 s12, s10
1040 ; GCN-IR-NEXT: s_subb_u32 s11, s11, s0
1041 ; GCN-IR-NEXT: s_add_i32 s12, s12, 32
1042 ; GCN-IR-NEXT: s_flbit_i32_b32 s13, s11
1043 ; GCN-IR-NEXT: v_mov_b32_e32 v1, s12
1044 ; GCN-IR-NEXT: s_flbit_i32_b32 s12, s8
1045 ; GCN-IR-NEXT: v_mov_b32_e32 v0, s13
1046 ; GCN-IR-NEXT: v_cmp_eq_u32_e64 vcc, s11, 0
1047 ; GCN-IR-NEXT: s_add_i32 s12, s12, 32
1048 ; GCN-IR-NEXT: s_flbit_i32_b32 s13, s9
1049 ; GCN-IR-NEXT: v_cndmask_b32_e32 v2, v0, v1, vcc
1050 ; GCN-IR-NEXT: v_mov_b32_e32 v0, s13
1051 ; GCN-IR-NEXT: v_mov_b32_e32 v1, s12
1052 ; GCN-IR-NEXT: v_cmp_eq_u32_e64 vcc, s9, 0
1053 ; GCN-IR-NEXT: v_cndmask_b32_e32 v3, v0, v1, vcc
1054 ; GCN-IR-NEXT: v_sub_i32_e32 v0, vcc, v2, v3
1055 ; GCN-IR-NEXT: v_subb_u32_e64 v1, s[12:13], 0, 0, vcc
1056 ; GCN-IR-NEXT: v_cmp_eq_u64_e64 s[0:1], s[10:11], 0
1057 ; GCN-IR-NEXT: v_cmp_eq_u64_e64 s[6:7], s[8:9], 0
1058 ; GCN-IR-NEXT: v_cmp_lt_u64_e32 vcc, 63, v[0:1]
1059 ; GCN-IR-NEXT: s_or_b64 s[0:1], s[0:1], s[6:7]
1060 ; GCN-IR-NEXT: s_or_b64 s[0:1], s[0:1], vcc
1061 ; GCN-IR-NEXT: v_cmp_ne_u64_e32 vcc, 63, v[0:1]
1062 ; GCN-IR-NEXT: s_xor_b64 s[6:7], s[0:1], -1
1063 ; GCN-IR-NEXT: s_and_b64 s[6:7], s[6:7], vcc
1064 ; GCN-IR-NEXT: s_and_b64 vcc, exec, s[6:7]
1065 ; GCN-IR-NEXT: s_cbranch_vccz BB8_4
1066 ; GCN-IR-NEXT: ; %bb.1: ; %udiv-bb1
1067 ; GCN-IR-NEXT: v_add_i32_e32 v4, vcc, 1, v0
1068 ; GCN-IR-NEXT: v_addc_u32_e32 v5, vcc, 0, v1, vcc
1069 ; GCN-IR-NEXT: v_cmp_lt_u64_e64 s[0:1], v[4:5], v[0:1]
1070 ; GCN-IR-NEXT: v_sub_i32_e32 v0, vcc, 63, v0
1071 ; GCN-IR-NEXT: v_lshl_b64 v[0:1], s[8:9], v0
1072 ; GCN-IR-NEXT: s_andn2_b64 vcc, exec, s[0:1]
1073 ; GCN-IR-NEXT: s_cbranch_vccz BB8_5
1074 ; GCN-IR-NEXT: ; %bb.2: ; %udiv-preheader
1075 ; GCN-IR-NEXT: v_not_b32_e32 v2, v2
1076 ; GCN-IR-NEXT: s_add_u32 s6, s10, -1
1077 ; GCN-IR-NEXT: v_lshr_b64 v[6:7], s[8:9], v4
1078 ; GCN-IR-NEXT: v_add_i32_e32 v4, vcc, v2, v3
1079 ; GCN-IR-NEXT: v_mov_b32_e32 v8, 0
1080 ; GCN-IR-NEXT: s_addc_u32 s7, s11, -1
1081 ; GCN-IR-NEXT: v_addc_u32_e64 v5, s[0:1], -1, 0, vcc
1082 ; GCN-IR-NEXT: v_mov_b32_e32 v9, 0
1083 ; GCN-IR-NEXT: v_mov_b32_e32 v3, 0
1084 ; GCN-IR-NEXT: BB8_3: ; %udiv-do-while
1085 ; GCN-IR-NEXT: ; =>This Inner Loop Header: Depth=1
1086 ; GCN-IR-NEXT: v_lshl_b64 v[6:7], v[6:7], 1
1087 ; GCN-IR-NEXT: v_lshrrev_b32_e32 v2, 31, v1
1088 ; GCN-IR-NEXT: v_lshl_b64 v[0:1], v[0:1], 1
1089 ; GCN-IR-NEXT: v_or_b32_e32 v6, v6, v2
1090 ; GCN-IR-NEXT: v_or_b32_e32 v0, v8, v0
1091 ; GCN-IR-NEXT: v_mov_b32_e32 v2, s7
1092 ; GCN-IR-NEXT: v_sub_i32_e32 v8, vcc, s6, v6
1093 ; GCN-IR-NEXT: v_subb_u32_e32 v2, vcc, v2, v7, vcc
1094 ; GCN-IR-NEXT: v_ashrrev_i32_e32 v8, 31, v2
1095 ; GCN-IR-NEXT: v_and_b32_e32 v10, s10, v8
1096 ; GCN-IR-NEXT: v_and_b32_e32 v2, 1, v8
1097 ; GCN-IR-NEXT: v_and_b32_e32 v11, s11, v8
1098 ; GCN-IR-NEXT: v_add_i32_e32 v8, vcc, 1, v4
1099 ; GCN-IR-NEXT: v_or_b32_e32 v1, v9, v1
1100 ; GCN-IR-NEXT: v_addc_u32_e32 v9, vcc, 0, v5, vcc
1101 ; GCN-IR-NEXT: v_cmp_lt_u64_e32 vcc, v[8:9], v[4:5]
1102 ; GCN-IR-NEXT: v_mov_b32_e32 v4, v8
1103 ; GCN-IR-NEXT: v_sub_i32_e64 v6, s[0:1], v6, v10
1104 ; GCN-IR-NEXT: v_mov_b32_e32 v5, v9
1105 ; GCN-IR-NEXT: v_mov_b32_e32 v9, v3
1106 ; GCN-IR-NEXT: v_subb_u32_e64 v7, s[0:1], v7, v11, s[0:1]
1107 ; GCN-IR-NEXT: s_and_b64 vcc, exec, vcc
1108 ; GCN-IR-NEXT: v_mov_b32_e32 v8, v2
1109 ; GCN-IR-NEXT: s_cbranch_vccz BB8_3
1110 ; GCN-IR-NEXT: s_branch BB8_6
1111 ; GCN-IR-NEXT: BB8_4:
1112 ; GCN-IR-NEXT: v_mov_b32_e32 v0, s9
1113 ; GCN-IR-NEXT: v_cndmask_b32_e64 v1, v0, 0, s[0:1]
1114 ; GCN-IR-NEXT: v_mov_b32_e32 v0, s8
1115 ; GCN-IR-NEXT: v_cndmask_b32_e64 v0, v0, 0, s[0:1]
1116 ; GCN-IR-NEXT: s_branch BB8_7
1117 ; GCN-IR-NEXT: BB8_5:
1118 ; GCN-IR-NEXT: v_mov_b32_e32 v2, 0
1119 ; GCN-IR-NEXT: v_mov_b32_e32 v3, 0
1120 ; GCN-IR-NEXT: BB8_6: ; %Flow6
1121 ; GCN-IR-NEXT: v_lshl_b64 v[0:1], v[0:1], 1
1122 ; GCN-IR-NEXT: v_or_b32_e32 v0, v2, v0
1123 ; GCN-IR-NEXT: v_or_b32_e32 v1, v3, v1
1124 ; GCN-IR-NEXT: BB8_7: ; %udiv-end
1125 ; GCN-IR-NEXT: v_mul_lo_u32 v1, s10, v1
1126 ; GCN-IR-NEXT: v_mul_hi_u32 v2, s10, v0
1127 ; GCN-IR-NEXT: v_mul_lo_u32 v3, s11, v0
1128 ; GCN-IR-NEXT: v_mul_lo_u32 v0, s10, v0
1129 ; GCN-IR-NEXT: s_mov_b32 s7, 0xf000
1130 ; GCN-IR-NEXT: v_add_i32_e32 v1, vcc, v2, v1
1131 ; GCN-IR-NEXT: v_add_i32_e32 v1, vcc, v1, v3
1132 ; GCN-IR-NEXT: v_sub_i32_e32 v0, vcc, s8, v0
1133 ; GCN-IR-NEXT: v_mov_b32_e32 v2, s9
1134 ; GCN-IR-NEXT: v_subb_u32_e32 v1, vcc, v2, v1, vcc
1135 ; GCN-IR-NEXT: v_xor_b32_e32 v0, s2, v0
1136 ; GCN-IR-NEXT: v_xor_b32_e32 v1, s3, v1
1137 ; GCN-IR-NEXT: v_mov_b32_e32 v2, s3
1138 ; GCN-IR-NEXT: v_subrev_i32_e32 v0, vcc, s2, v0
1139 ; GCN-IR-NEXT: s_mov_b32 s6, -1
1140 ; GCN-IR-NEXT: v_subb_u32_e32 v1, vcc, v1, v2, vcc
1141 ; GCN-IR-NEXT: buffer_store_dwordx2 v[0:1], off, s[4:7], 0
1142 ; GCN-IR-NEXT: s_endpgm
1188 ; GCN-IR-LABEL: s_test_srem24_48:
1189 ; GCN-IR: ; %bb.0: ; %_udiv-special-cases
1190 ; GCN-IR-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x9
1191 ; GCN-IR-NEXT: s_load_dword s2, s[0:1], 0xb
1192 ; GCN-IR-NEXT: s_load_dword s3, s[0:1], 0xc
1193 ; GCN-IR-NEXT: s_load_dword s6, s[0:1], 0xd
1194 ; GCN-IR-NEXT: s_load_dword s0, s[0:1], 0xe
1195 ; GCN-IR-NEXT: s_waitcnt lgkmcnt(0)
1196 ; GCN-IR-NEXT: s_sext_i32_i16 s3, s3
1197 ; GCN-IR-NEXT: s_sext_i32_i16 s7, s0
1198 ; GCN-IR-NEXT: s_ashr_i64 s[0:1], s[2:3], 24
1199 ; GCN-IR-NEXT: s_ashr_i32 s2, s3, 31
1200 ; GCN-IR-NEXT: s_ashr_i32 s10, s7, 31
1201 ; GCN-IR-NEXT: s_mov_b32 s3, s2
1202 ; GCN-IR-NEXT: s_ashr_i64 s[8:9], s[6:7], 24
1203 ; GCN-IR-NEXT: s_mov_b32 s11, s10
1204 ; GCN-IR-NEXT: s_xor_b64 s[0:1], s[0:1], s[2:3]
1205 ; GCN-IR-NEXT: s_xor_b64 s[8:9], s[8:9], s[10:11]
1206 ; GCN-IR-NEXT: s_sub_u32 s6, s0, s2
1207 ; GCN-IR-NEXT: s_subb_u32 s7, s1, s2
1208 ; GCN-IR-NEXT: s_sub_u32 s8, s8, s10
1209 ; GCN-IR-NEXT: s_flbit_i32_b32 s12, s8
1210 ; GCN-IR-NEXT: s_subb_u32 s9, s9, s10
1211 ; GCN-IR-NEXT: s_add_i32 s12, s12, 32
1212 ; GCN-IR-NEXT: s_flbit_i32_b32 s13, s9
1213 ; GCN-IR-NEXT: v_mov_b32_e32 v1, s12
1214 ; GCN-IR-NEXT: s_flbit_i32_b32 s12, s6
1215 ; GCN-IR-NEXT: v_mov_b32_e32 v0, s13
1216 ; GCN-IR-NEXT: v_cmp_eq_u32_e64 vcc, s9, 0
1217 ; GCN-IR-NEXT: s_add_i32 s12, s12, 32
1218 ; GCN-IR-NEXT: s_flbit_i32_b32 s13, s7
1219 ; GCN-IR-NEXT: v_cndmask_b32_e32 v2, v0, v1, vcc
1220 ; GCN-IR-NEXT: v_mov_b32_e32 v0, s13
1221 ; GCN-IR-NEXT: v_mov_b32_e32 v1, s12
1222 ; GCN-IR-NEXT: v_cmp_eq_u32_e64 vcc, s7, 0
1223 ; GCN-IR-NEXT: v_cndmask_b32_e32 v3, v0, v1, vcc
1224 ; GCN-IR-NEXT: v_sub_i32_e32 v0, vcc, v2, v3
1225 ; GCN-IR-NEXT: v_subb_u32_e64 v1, s[12:13], 0, 0, vcc
1226 ; GCN-IR-NEXT: v_cmp_eq_u64_e64 s[0:1], s[8:9], 0
1227 ; GCN-IR-NEXT: v_cmp_eq_u64_e64 s[10:11], s[6:7], 0
1228 ; GCN-IR-NEXT: v_cmp_lt_u64_e32 vcc, 63, v[0:1]
1229 ; GCN-IR-NEXT: s_or_b64 s[0:1], s[0:1], s[10:11]
1230 ; GCN-IR-NEXT: s_or_b64 s[0:1], s[0:1], vcc
1231 ; GCN-IR-NEXT: v_cmp_ne_u64_e32 vcc, 63, v[0:1]
1232 ; GCN-IR-NEXT: s_xor_b64 s[10:11], s[0:1], -1
1233 ; GCN-IR-NEXT: s_and_b64 s[10:11], s[10:11], vcc
1234 ; GCN-IR-NEXT: s_and_b64 vcc, exec, s[10:11]
1235 ; GCN-IR-NEXT: s_cbranch_vccz BB9_4
1236 ; GCN-IR-NEXT: ; %bb.1: ; %udiv-bb1
1237 ; GCN-IR-NEXT: v_add_i32_e32 v4, vcc, 1, v0
1238 ; GCN-IR-NEXT: v_addc_u32_e32 v5, vcc, 0, v1, vcc
1239 ; GCN-IR-NEXT: v_cmp_lt_u64_e64 s[0:1], v[4:5], v[0:1]
1240 ; GCN-IR-NEXT: v_sub_i32_e32 v0, vcc, 63, v0
1241 ; GCN-IR-NEXT: v_lshl_b64 v[0:1], s[6:7], v0
1242 ; GCN-IR-NEXT: s_andn2_b64 vcc, exec, s[0:1]
1243 ; GCN-IR-NEXT: s_cbranch_vccz BB9_5
1244 ; GCN-IR-NEXT: ; %bb.2: ; %udiv-preheader
1245 ; GCN-IR-NEXT: v_not_b32_e32 v2, v2
1246 ; GCN-IR-NEXT: s_add_u32 s10, s8, -1
1247 ; GCN-IR-NEXT: v_lshr_b64 v[6:7], s[6:7], v4
1248 ; GCN-IR-NEXT: v_add_i32_e32 v4, vcc, v2, v3
1249 ; GCN-IR-NEXT: v_mov_b32_e32 v8, 0
1250 ; GCN-IR-NEXT: s_addc_u32 s11, s9, -1
1251 ; GCN-IR-NEXT: v_addc_u32_e64 v5, s[0:1], -1, 0, vcc
1252 ; GCN-IR-NEXT: v_mov_b32_e32 v9, 0
1253 ; GCN-IR-NEXT: v_mov_b32_e32 v3, 0
1254 ; GCN-IR-NEXT: BB9_3: ; %udiv-do-while
1255 ; GCN-IR-NEXT: ; =>This Inner Loop Header: Depth=1
1256 ; GCN-IR-NEXT: v_lshl_b64 v[6:7], v[6:7], 1
1257 ; GCN-IR-NEXT: v_lshrrev_b32_e32 v2, 31, v1
1258 ; GCN-IR-NEXT: v_lshl_b64 v[0:1], v[0:1], 1
1259 ; GCN-IR-NEXT: v_or_b32_e32 v6, v6, v2
1260 ; GCN-IR-NEXT: v_or_b32_e32 v0, v8, v0
1261 ; GCN-IR-NEXT: v_mov_b32_e32 v2, s11
1262 ; GCN-IR-NEXT: v_sub_i32_e32 v8, vcc, s10, v6
1263 ; GCN-IR-NEXT: v_subb_u32_e32 v2, vcc, v2, v7, vcc
1264 ; GCN-IR-NEXT: v_ashrrev_i32_e32 v8, 31, v2
1265 ; GCN-IR-NEXT: v_and_b32_e32 v10, s8, v8
1266 ; GCN-IR-NEXT: v_and_b32_e32 v2, 1, v8
1267 ; GCN-IR-NEXT: v_and_b32_e32 v11, s9, v8
1268 ; GCN-IR-NEXT: v_add_i32_e32 v8, vcc, 1, v4
1269 ; GCN-IR-NEXT: v_or_b32_e32 v1, v9, v1
1270 ; GCN-IR-NEXT: v_addc_u32_e32 v9, vcc, 0, v5, vcc
1271 ; GCN-IR-NEXT: v_cmp_lt_u64_e32 vcc, v[8:9], v[4:5]
1272 ; GCN-IR-NEXT: v_mov_b32_e32 v4, v8
1273 ; GCN-IR-NEXT: v_sub_i32_e64 v6, s[0:1], v6, v10
1274 ; GCN-IR-NEXT: v_mov_b32_e32 v5, v9
1275 ; GCN-IR-NEXT: v_mov_b32_e32 v9, v3
1276 ; GCN-IR-NEXT: v_subb_u32_e64 v7, s[0:1], v7, v11, s[0:1]
1277 ; GCN-IR-NEXT: s_and_b64 vcc, exec, vcc
1278 ; GCN-IR-NEXT: v_mov_b32_e32 v8, v2
1279 ; GCN-IR-NEXT: s_cbranch_vccz BB9_3
1280 ; GCN-IR-NEXT: s_branch BB9_6
1281 ; GCN-IR-NEXT: BB9_4:
1282 ; GCN-IR-NEXT: v_mov_b32_e32 v0, s7
1283 ; GCN-IR-NEXT: v_cndmask_b32_e64 v1, v0, 0, s[0:1]
1284 ; GCN-IR-NEXT: v_mov_b32_e32 v0, s6
1285 ; GCN-IR-NEXT: v_cndmask_b32_e64 v0, v0, 0, s[0:1]
1286 ; GCN-IR-NEXT: s_branch BB9_7
1287 ; GCN-IR-NEXT: BB9_5:
1288 ; GCN-IR-NEXT: v_mov_b32_e32 v2, 0
1289 ; GCN-IR-NEXT: v_mov_b32_e32 v3, 0
1290 ; GCN-IR-NEXT: BB9_6: ; %Flow3
1291 ; GCN-IR-NEXT: v_lshl_b64 v[0:1], v[0:1], 1
1292 ; GCN-IR-NEXT: v_or_b32_e32 v0, v2, v0
1293 ; GCN-IR-NEXT: v_or_b32_e32 v1, v3, v1
1294 ; GCN-IR-NEXT: BB9_7: ; %udiv-end
1295 ; GCN-IR-NEXT: v_mul_lo_u32 v1, s8, v1
1296 ; GCN-IR-NEXT: v_mul_hi_u32 v2, s8, v0
1297 ; GCN-IR-NEXT: v_mul_lo_u32 v3, s9, v0
1298 ; GCN-IR-NEXT: v_mul_lo_u32 v0, s8, v0
1299 ; GCN-IR-NEXT: v_add_i32_e32 v1, vcc, v2, v1
1300 ; GCN-IR-NEXT: v_add_i32_e32 v1, vcc, v1, v3
1301 ; GCN-IR-NEXT: v_sub_i32_e32 v0, vcc, s6, v0
1302 ; GCN-IR-NEXT: v_mov_b32_e32 v2, s7
1303 ; GCN-IR-NEXT: v_subb_u32_e32 v1, vcc, v2, v1, vcc
1304 ; GCN-IR-NEXT: v_xor_b32_e32 v0, s2, v0
1305 ; GCN-IR-NEXT: v_xor_b32_e32 v1, s3, v1
1306 ; GCN-IR-NEXT: v_mov_b32_e32 v2, s3
1307 ; GCN-IR-NEXT: v_subrev_i32_e32 v0, vcc, s2, v0
1308 ; GCN-IR-NEXT: v_subb_u32_e32 v1, vcc, v1, v2, vcc
1309 ; GCN-IR-NEXT: s_mov_b32 s7, 0xf000
1310 ; GCN-IR-NEXT: s_mov_b32 s6, -1
1311 ; GCN-IR-NEXT: buffer_store_short v1, off, s[4:7], 0 offset:4
1312 ; GCN-IR-NEXT: buffer_store_dword v0, off, s[4:7], 0
1313 ; GCN-IR-NEXT: s_endpgm
1440 ; GCN-IR-LABEL: s_test_srem_k_num_i64:
1441 ; GCN-IR: ; %bb.0: ; %_udiv-special-cases
1442 ; GCN-IR-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x9
1443 ; GCN-IR-NEXT: s_waitcnt lgkmcnt(0)
1444 ; GCN-IR-NEXT: s_ashr_i32 s0, s7, 31
1445 ; GCN-IR-NEXT: s_mov_b32 s1, s0
1446 ; GCN-IR-NEXT: s_xor_b64 s[2:3], s[6:7], s[0:1]
1447 ; GCN-IR-NEXT: s_sub_u32 s2, s2, s0
1448 ; GCN-IR-NEXT: s_subb_u32 s3, s3, s0
1449 ; GCN-IR-NEXT: s_flbit_i32_b32 s6, s2
1450 ; GCN-IR-NEXT: s_add_i32 s6, s6, 32
1451 ; GCN-IR-NEXT: s_flbit_i32_b32 s7, s3
1452 ; GCN-IR-NEXT: v_mov_b32_e32 v0, s7
1453 ; GCN-IR-NEXT: v_mov_b32_e32 v1, s6
1454 ; GCN-IR-NEXT: v_cmp_eq_u32_e64 vcc, s3, 0
1455 ; GCN-IR-NEXT: v_cndmask_b32_e32 v2, v0, v1, vcc
1456 ; GCN-IR-NEXT: v_add_i32_e32 v0, vcc, 0xffffffc5, v2
1457 ; GCN-IR-NEXT: v_addc_u32_e64 v1, s[6:7], 0, -1, vcc
1458 ; GCN-IR-NEXT: v_cmp_eq_u64_e64 s[0:1], s[2:3], 0
1459 ; GCN-IR-NEXT: v_cmp_lt_u64_e32 vcc, 63, v[0:1]
1460 ; GCN-IR-NEXT: s_or_b64 s[0:1], s[0:1], vcc
1461 ; GCN-IR-NEXT: v_cmp_ne_u64_e32 vcc, 63, v[0:1]
1462 ; GCN-IR-NEXT: s_xor_b64 s[6:7], s[0:1], -1
1463 ; GCN-IR-NEXT: s_and_b64 s[6:7], s[6:7], vcc
1464 ; GCN-IR-NEXT: s_and_b64 vcc, exec, s[6:7]
1465 ; GCN-IR-NEXT: s_cbranch_vccz BB10_4
1466 ; GCN-IR-NEXT: ; %bb.1: ; %udiv-bb1
1467 ; GCN-IR-NEXT: v_add_i32_e32 v3, vcc, 1, v0
1468 ; GCN-IR-NEXT: v_addc_u32_e32 v4, vcc, 0, v1, vcc
1469 ; GCN-IR-NEXT: v_cmp_lt_u64_e64 s[0:1], v[3:4], v[0:1]
1470 ; GCN-IR-NEXT: v_sub_i32_e32 v0, vcc, 63, v0
1471 ; GCN-IR-NEXT: v_lshl_b64 v[0:1], 24, v0
1472 ; GCN-IR-NEXT: s_andn2_b64 vcc, exec, s[0:1]
1473 ; GCN-IR-NEXT: s_cbranch_vccz BB10_5
1474 ; GCN-IR-NEXT: ; %bb.2: ; %udiv-preheader
1475 ; GCN-IR-NEXT: s_add_u32 s6, s2, -1
1476 ; GCN-IR-NEXT: v_lshr_b64 v[6:7], 24, v3
1477 ; GCN-IR-NEXT: v_sub_i32_e32 v4, vcc, 58, v2
1478 ; GCN-IR-NEXT: v_mov_b32_e32 v8, 0
1479 ; GCN-IR-NEXT: s_addc_u32 s7, s3, -1
1480 ; GCN-IR-NEXT: v_subb_u32_e64 v5, s[0:1], 0, 0, vcc
1481 ; GCN-IR-NEXT: v_mov_b32_e32 v9, 0
1482 ; GCN-IR-NEXT: v_mov_b32_e32 v3, 0
1483 ; GCN-IR-NEXT: BB10_3: ; %udiv-do-while
1484 ; GCN-IR-NEXT: ; =>This Inner Loop Header: Depth=1
1485 ; GCN-IR-NEXT: v_lshl_b64 v[6:7], v[6:7], 1
1486 ; GCN-IR-NEXT: v_lshrrev_b32_e32 v2, 31, v1
1487 ; GCN-IR-NEXT: v_lshl_b64 v[0:1], v[0:1], 1
1488 ; GCN-IR-NEXT: v_or_b32_e32 v6, v6, v2
1489 ; GCN-IR-NEXT: v_or_b32_e32 v0, v8, v0
1490 ; GCN-IR-NEXT: v_mov_b32_e32 v2, s7
1491 ; GCN-IR-NEXT: v_sub_i32_e32 v8, vcc, s6, v6
1492 ; GCN-IR-NEXT: v_subb_u32_e32 v2, vcc, v2, v7, vcc
1493 ; GCN-IR-NEXT: v_ashrrev_i32_e32 v8, 31, v2
1494 ; GCN-IR-NEXT: v_and_b32_e32 v10, s2, v8
1495 ; GCN-IR-NEXT: v_and_b32_e32 v2, 1, v8
1496 ; GCN-IR-NEXT: v_and_b32_e32 v11, s3, v8
1497 ; GCN-IR-NEXT: v_add_i32_e32 v8, vcc, 1, v4
1498 ; GCN-IR-NEXT: v_or_b32_e32 v1, v9, v1
1499 ; GCN-IR-NEXT: v_addc_u32_e32 v9, vcc, 0, v5, vcc
1500 ; GCN-IR-NEXT: v_cmp_lt_u64_e32 vcc, v[8:9], v[4:5]
1501 ; GCN-IR-NEXT: v_mov_b32_e32 v4, v8
1502 ; GCN-IR-NEXT: v_sub_i32_e64 v6, s[0:1], v6, v10
1503 ; GCN-IR-NEXT: v_mov_b32_e32 v5, v9
1504 ; GCN-IR-NEXT: v_mov_b32_e32 v9, v3
1505 ; GCN-IR-NEXT: v_subb_u32_e64 v7, s[0:1], v7, v11, s[0:1]
1506 ; GCN-IR-NEXT: s_and_b64 vcc, exec, vcc
1507 ; GCN-IR-NEXT: v_mov_b32_e32 v8, v2
1508 ; GCN-IR-NEXT: s_cbranch_vccz BB10_3
1509 ; GCN-IR-NEXT: s_branch BB10_6
1510 ; GCN-IR-NEXT: BB10_4:
1511 ; GCN-IR-NEXT: v_mov_b32_e32 v1, 0
1512 ; GCN-IR-NEXT: v_cndmask_b32_e64 v0, 24, 0, s[0:1]
1513 ; GCN-IR-NEXT: s_branch BB10_7
1514 ; GCN-IR-NEXT: BB10_5:
1515 ; GCN-IR-NEXT: v_mov_b32_e32 v2, 0
1516 ; GCN-IR-NEXT: v_mov_b32_e32 v3, 0
1517 ; GCN-IR-NEXT: BB10_6: ; %Flow5
1518 ; GCN-IR-NEXT: v_lshl_b64 v[0:1], v[0:1], 1
1519 ; GCN-IR-NEXT: v_or_b32_e32 v0, v2, v0
1520 ; GCN-IR-NEXT: v_or_b32_e32 v1, v3, v1
1521 ; GCN-IR-NEXT: BB10_7: ; %udiv-end
1522 ; GCN-IR-NEXT: v_mul_lo_u32 v1, s2, v1
1523 ; GCN-IR-NEXT: v_mul_hi_u32 v2, s2, v0
1524 ; GCN-IR-NEXT: v_mul_lo_u32 v3, s3, v0
1525 ; GCN-IR-NEXT: v_mul_lo_u32 v0, s2, v0
1526 ; GCN-IR-NEXT: s_mov_b32 s7, 0xf000
1527 ; GCN-IR-NEXT: v_add_i32_e32 v1, vcc, v2, v1
1528 ; GCN-IR-NEXT: v_add_i32_e32 v1, vcc, v1, v3
1529 ; GCN-IR-NEXT: v_sub_i32_e32 v0, vcc, 24, v0
1530 ; GCN-IR-NEXT: s_mov_b32 s6, -1
1531 ; GCN-IR-NEXT: v_subb_u32_e32 v1, vcc, 0, v1, vcc
1532 ; GCN-IR-NEXT: buffer_store_dwordx2 v[0:1], off, s[4:7], 0
1533 ; GCN-IR-NEXT: s_endpgm
1653 ; GCN-IR-LABEL: v_test_srem_k_num_i64:
1654 ; GCN-IR: ; %bb.0: ; %_udiv-special-cases
1655 ; GCN-IR-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
1656 ; GCN-IR-NEXT: v_ashrrev_i32_e32 v2, 31, v1
1657 ; GCN-IR-NEXT: v_xor_b32_e32 v0, v0, v2
1658 ; GCN-IR-NEXT: v_xor_b32_e32 v1, v1, v2
1659 ; GCN-IR-NEXT: v_sub_i32_e32 v0, vcc, v0, v2
1660 ; GCN-IR-NEXT: v_subb_u32_e32 v1, vcc, v1, v2, vcc
1661 ; GCN-IR-NEXT: v_ffbh_u32_e32 v2, v0
1662 ; GCN-IR-NEXT: v_add_i32_e32 v2, vcc, 32, v2
1663 ; GCN-IR-NEXT: v_ffbh_u32_e32 v3, v1
1664 ; GCN-IR-NEXT: v_cmp_eq_u32_e32 vcc, 0, v1
1665 ; GCN-IR-NEXT: v_cndmask_b32_e32 v8, v3, v2, vcc
1666 ; GCN-IR-NEXT: s_movk_i32 s6, 0xffc5
1667 ; GCN-IR-NEXT: v_add_i32_e32 v3, vcc, s6, v8
1668 ; GCN-IR-NEXT: v_addc_u32_e64 v4, s[6:7], 0, -1, vcc
1669 ; GCN-IR-NEXT: v_cmp_eq_u64_e64 s[4:5], 0, v[0:1]
1670 ; GCN-IR-NEXT: v_cmp_lt_u64_e32 vcc, 63, v[3:4]
1671 ; GCN-IR-NEXT: v_mov_b32_e32 v9, 0
1672 ; GCN-IR-NEXT: s_or_b64 s[4:5], s[4:5], vcc
1673 ; GCN-IR-NEXT: v_cmp_ne_u64_e32 vcc, 63, v[3:4]
1674 ; GCN-IR-NEXT: v_cndmask_b32_e64 v2, 24, 0, s[4:5]
1675 ; GCN-IR-NEXT: s_xor_b64 s[4:5], s[4:5], -1
1676 ; GCN-IR-NEXT: v_mov_b32_e32 v5, v9
1677 ; GCN-IR-NEXT: s_and_b64 s[4:5], s[4:5], vcc
1678 ; GCN-IR-NEXT: s_and_saveexec_b64 s[6:7], s[4:5]
1679 ; GCN-IR-NEXT: s_cbranch_execz BB11_6
1680 ; GCN-IR-NEXT: ; %bb.1: ; %udiv-bb1
1681 ; GCN-IR-NEXT: v_add_i32_e32 v6, vcc, 1, v3
1682 ; GCN-IR-NEXT: v_addc_u32_e32 v7, vcc, 0, v4, vcc
1683 ; GCN-IR-NEXT: v_sub_i32_e64 v2, s[4:5], 63, v3
1684 ; GCN-IR-NEXT: v_cmp_ge_u64_e32 vcc, v[6:7], v[3:4]
1685 ; GCN-IR-NEXT: v_mov_b32_e32 v4, 0
1686 ; GCN-IR-NEXT: v_lshl_b64 v[2:3], 24, v2
1687 ; GCN-IR-NEXT: s_mov_b64 s[8:9], 0
1688 ; GCN-IR-NEXT: v_mov_b32_e32 v5, 0
1689 ; GCN-IR-NEXT: s_and_saveexec_b64 s[4:5], vcc
1690 ; GCN-IR-NEXT: s_xor_b64 s[10:11], exec, s[4:5]
1691 ; GCN-IR-NEXT: s_cbranch_execz BB11_5
1692 ; GCN-IR-NEXT: ; %bb.2: ; %udiv-preheader
1693 ; GCN-IR-NEXT: v_lshr_b64 v[10:11], 24, v6
1694 ; GCN-IR-NEXT: v_add_i32_e32 v6, vcc, -1, v0
1695 ; GCN-IR-NEXT: v_addc_u32_e32 v7, vcc, -1, v1, vcc
1696 ; GCN-IR-NEXT: v_sub_i32_e32 v8, vcc, 58, v8
1697 ; GCN-IR-NEXT: v_mov_b32_e32 v12, 0
1698 ; GCN-IR-NEXT: v_subb_u32_e32 v9, vcc, 0, v9, vcc
1699 ; GCN-IR-NEXT: v_mov_b32_e32 v13, 0
1700 ; GCN-IR-NEXT: BB11_3: ; %udiv-do-while
1701 ; GCN-IR-NEXT: ; =>This Inner Loop Header: Depth=1
1702 ; GCN-IR-NEXT: v_lshl_b64 v[10:11], v[10:11], 1
1703 ; GCN-IR-NEXT: v_lshrrev_b32_e32 v4, 31, v3
1704 ; GCN-IR-NEXT: v_or_b32_e32 v10, v10, v4
1705 ; GCN-IR-NEXT: v_lshl_b64 v[2:3], v[2:3], 1
1706 ; GCN-IR-NEXT: v_sub_i32_e32 v4, vcc, v6, v10
1707 ; GCN-IR-NEXT: v_subb_u32_e32 v4, vcc, v7, v11, vcc
1708 ; GCN-IR-NEXT: v_or_b32_e32 v2, v12, v2
1709 ; GCN-IR-NEXT: v_ashrrev_i32_e32 v12, 31, v4
1710 ; GCN-IR-NEXT: v_and_b32_e32 v15, v12, v0
1711 ; GCN-IR-NEXT: v_and_b32_e32 v4, 1, v12
1712 ; GCN-IR-NEXT: v_and_b32_e32 v14, v12, v1
1713 ; GCN-IR-NEXT: v_add_i32_e32 v12, vcc, 1, v8
1714 ; GCN-IR-NEXT: v_or_b32_e32 v3, v13, v3
1715 ; GCN-IR-NEXT: v_addc_u32_e32 v13, vcc, 0, v9, vcc
1716 ; GCN-IR-NEXT: v_cmp_lt_u64_e32 vcc, v[12:13], v[8:9]
1717 ; GCN-IR-NEXT: v_mov_b32_e32 v8, v12
1718 ; GCN-IR-NEXT: v_mov_b32_e32 v5, 0
1719 ; GCN-IR-NEXT: v_sub_i32_e64 v10, s[4:5], v10, v15
1720 ; GCN-IR-NEXT: v_mov_b32_e32 v9, v13
1721 ; GCN-IR-NEXT: v_mov_b32_e32 v13, v5
1722 ; GCN-IR-NEXT: v_subb_u32_e64 v11, s[4:5], v11, v14, s[4:5]
1723 ; GCN-IR-NEXT: s_or_b64 s[8:9], vcc, s[8:9]
1724 ; GCN-IR-NEXT: v_mov_b32_e32 v12, v4
1725 ; GCN-IR-NEXT: s_andn2_b64 exec, exec, s[8:9]
1726 ; GCN-IR-NEXT: s_cbranch_execnz BB11_3
1727 ; GCN-IR-NEXT: ; %bb.4: ; %Flow
1728 ; GCN-IR-NEXT: s_or_b64 exec, exec, s[8:9]
1729 ; GCN-IR-NEXT: BB11_5: ; %Flow3
1730 ; GCN-IR-NEXT: s_or_b64 exec, exec, s[10:11]
1731 ; GCN-IR-NEXT: v_lshl_b64 v[2:3], v[2:3], 1
1732 ; GCN-IR-NEXT: v_or_b32_e32 v5, v5, v3
1733 ; GCN-IR-NEXT: v_or_b32_e32 v2, v4, v2
1734 ; GCN-IR-NEXT: BB11_6: ; %Flow4
1735 ; GCN-IR-NEXT: s_or_b64 exec, exec, s[6:7]
1736 ; GCN-IR-NEXT: v_mul_lo_u32 v3, v0, v5
1737 ; GCN-IR-NEXT: v_mul_hi_u32 v4, v0, v2
1738 ; GCN-IR-NEXT: v_mul_lo_u32 v1, v1, v2
1739 ; GCN-IR-NEXT: v_mul_lo_u32 v0, v0, v2
1740 ; GCN-IR-NEXT: v_add_i32_e32 v3, vcc, v4, v3
1741 ; GCN-IR-NEXT: v_add_i32_e32 v1, vcc, v3, v1
1742 ; GCN-IR-NEXT: v_sub_i32_e32 v0, vcc, 24, v0
1743 ; GCN-IR-NEXT: v_subb_u32_e32 v1, vcc, 0, v1, vcc
1744 ; GCN-IR-NEXT: s_setpc_b64 s[30:31]
1864 ; GCN-IR-LABEL: v_test_srem_pow2_k_num_i64:
1865 ; GCN-IR: ; %bb.0: ; %_udiv-special-cases
1866 ; GCN-IR-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
1867 ; GCN-IR-NEXT: v_ashrrev_i32_e32 v2, 31, v1
1868 ; GCN-IR-NEXT: v_xor_b32_e32 v0, v0, v2
1869 ; GCN-IR-NEXT: v_xor_b32_e32 v1, v1, v2
1870 ; GCN-IR-NEXT: v_sub_i32_e32 v0, vcc, v0, v2
1871 ; GCN-IR-NEXT: v_subb_u32_e32 v1, vcc, v1, v2, vcc
1872 ; GCN-IR-NEXT: v_ffbh_u32_e32 v2, v0
1873 ; GCN-IR-NEXT: v_add_i32_e32 v2, vcc, 32, v2
1874 ; GCN-IR-NEXT: v_ffbh_u32_e32 v3, v1
1875 ; GCN-IR-NEXT: v_cmp_eq_u32_e32 vcc, 0, v1
1876 ; GCN-IR-NEXT: v_cndmask_b32_e32 v8, v3, v2, vcc
1877 ; GCN-IR-NEXT: s_movk_i32 s6, 0xffd0
1878 ; GCN-IR-NEXT: v_add_i32_e32 v2, vcc, s6, v8
1879 ; GCN-IR-NEXT: v_addc_u32_e64 v3, s[6:7], 0, -1, vcc
1880 ; GCN-IR-NEXT: v_cmp_eq_u64_e64 s[4:5], 0, v[0:1]
1881 ; GCN-IR-NEXT: v_cmp_lt_u64_e32 vcc, 63, v[2:3]
1882 ; GCN-IR-NEXT: s_mov_b32 s8, 0x8000
1883 ; GCN-IR-NEXT: s_or_b64 s[4:5], s[4:5], vcc
1884 ; GCN-IR-NEXT: v_mov_b32_e32 v4, s8
1885 ; GCN-IR-NEXT: v_cmp_ne_u64_e32 vcc, 63, v[2:3]
1886 ; GCN-IR-NEXT: v_mov_b32_e32 v9, 0
1887 ; GCN-IR-NEXT: v_cndmask_b32_e64 v4, v4, 0, s[4:5]
1888 ; GCN-IR-NEXT: s_xor_b64 s[4:5], s[4:5], -1
1889 ; GCN-IR-NEXT: s_mov_b32 s9, 0
1890 ; GCN-IR-NEXT: v_mov_b32_e32 v5, v9
1891 ; GCN-IR-NEXT: s_and_b64 s[4:5], s[4:5], vcc
1892 ; GCN-IR-NEXT: s_and_saveexec_b64 s[6:7], s[4:5]
1893 ; GCN-IR-NEXT: s_cbranch_execz BB12_6
1894 ; GCN-IR-NEXT: ; %bb.1: ; %udiv-bb1
1895 ; GCN-IR-NEXT: v_add_i32_e32 v6, vcc, 1, v2
1896 ; GCN-IR-NEXT: v_addc_u32_e32 v7, vcc, 0, v3, vcc
1897 ; GCN-IR-NEXT: v_cmp_ge_u64_e32 vcc, v[6:7], v[2:3]
1898 ; GCN-IR-NEXT: v_sub_i32_e64 v2, s[4:5], 63, v2
1899 ; GCN-IR-NEXT: v_lshl_b64 v[2:3], s[8:9], v2
1900 ; GCN-IR-NEXT: v_mov_b32_e32 v4, 0
1901 ; GCN-IR-NEXT: s_mov_b64 s[8:9], 0
1902 ; GCN-IR-NEXT: v_mov_b32_e32 v5, 0
1903 ; GCN-IR-NEXT: s_and_saveexec_b64 s[4:5], vcc
1904 ; GCN-IR-NEXT: s_xor_b64 s[10:11], exec, s[4:5]
1905 ; GCN-IR-NEXT: s_cbranch_execz BB12_5
1906 ; GCN-IR-NEXT: ; %bb.2: ; %udiv-preheader
1907 ; GCN-IR-NEXT: s_mov_b32 s5, 0
1908 ; GCN-IR-NEXT: s_mov_b32 s4, 0x8000
1909 ; GCN-IR-NEXT: v_lshr_b64 v[10:11], s[4:5], v6
1910 ; GCN-IR-NEXT: v_add_i32_e32 v6, vcc, -1, v0
1911 ; GCN-IR-NEXT: v_addc_u32_e32 v7, vcc, -1, v1, vcc
1912 ; GCN-IR-NEXT: v_sub_i32_e32 v8, vcc, 47, v8
1913 ; GCN-IR-NEXT: v_mov_b32_e32 v12, 0
1914 ; GCN-IR-NEXT: v_subb_u32_e32 v9, vcc, 0, v9, vcc
1915 ; GCN-IR-NEXT: v_mov_b32_e32 v13, 0
1916 ; GCN-IR-NEXT: BB12_3: ; %udiv-do-while
1917 ; GCN-IR-NEXT: ; =>This Inner Loop Header: Depth=1
1918 ; GCN-IR-NEXT: v_lshl_b64 v[10:11], v[10:11], 1
1919 ; GCN-IR-NEXT: v_lshrrev_b32_e32 v4, 31, v3
1920 ; GCN-IR-NEXT: v_or_b32_e32 v10, v10, v4
1921 ; GCN-IR-NEXT: v_lshl_b64 v[2:3], v[2:3], 1
1922 ; GCN-IR-NEXT: v_sub_i32_e32 v4, vcc, v6, v10
1923 ; GCN-IR-NEXT: v_subb_u32_e32 v4, vcc, v7, v11, vcc
1924 ; GCN-IR-NEXT: v_or_b32_e32 v2, v12, v2
1925 ; GCN-IR-NEXT: v_ashrrev_i32_e32 v12, 31, v4
1926 ; GCN-IR-NEXT: v_and_b32_e32 v15, v12, v0
1927 ; GCN-IR-NEXT: v_and_b32_e32 v4, 1, v12
1928 ; GCN-IR-NEXT: v_and_b32_e32 v14, v12, v1
1929 ; GCN-IR-NEXT: v_add_i32_e32 v12, vcc, 1, v8
1930 ; GCN-IR-NEXT: v_or_b32_e32 v3, v13, v3
1931 ; GCN-IR-NEXT: v_addc_u32_e32 v13, vcc, 0, v9, vcc
1932 ; GCN-IR-NEXT: v_cmp_lt_u64_e32 vcc, v[12:13], v[8:9]
1933 ; GCN-IR-NEXT: v_mov_b32_e32 v8, v12
1934 ; GCN-IR-NEXT: v_mov_b32_e32 v5, 0
1935 ; GCN-IR-NEXT: v_sub_i32_e64 v10, s[4:5], v10, v15
1936 ; GCN-IR-NEXT: v_mov_b32_e32 v9, v13
1937 ; GCN-IR-NEXT: v_mov_b32_e32 v13, v5
1938 ; GCN-IR-NEXT: v_subb_u32_e64 v11, s[4:5], v11, v14, s[4:5]
1939 ; GCN-IR-NEXT: s_or_b64 s[8:9], vcc, s[8:9]
1940 ; GCN-IR-NEXT: v_mov_b32_e32 v12, v4
1941 ; GCN-IR-NEXT: s_andn2_b64 exec, exec, s[8:9]
1942 ; GCN-IR-NEXT: s_cbranch_execnz BB12_3
1943 ; GCN-IR-NEXT: ; %bb.4: ; %Flow
1944 ; GCN-IR-NEXT: s_or_b64 exec, exec, s[8:9]
1945 ; GCN-IR-NEXT: BB12_5: ; %Flow3
1946 ; GCN-IR-NEXT: s_or_b64 exec, exec, s[10:11]
1947 ; GCN-IR-NEXT: v_lshl_b64 v[2:3], v[2:3], 1
1948 ; GCN-IR-NEXT: v_or_b32_e32 v5, v5, v3
1949 ; GCN-IR-NEXT: v_or_b32_e32 v4, v4, v2
1950 ; GCN-IR-NEXT: BB12_6: ; %Flow4
1951 ; GCN-IR-NEXT: s_or_b64 exec, exec, s[6:7]
1952 ; GCN-IR-NEXT: v_mul_lo_u32 v2, v0, v5
1953 ; GCN-IR-NEXT: v_mul_hi_u32 v3, v0, v4
1954 ; GCN-IR-NEXT: v_mul_lo_u32 v1, v1, v4
1955 ; GCN-IR-NEXT: v_mul_lo_u32 v0, v0, v4
1956 ; GCN-IR-NEXT: v_add_i32_e32 v2, vcc, v3, v2
1957 ; GCN-IR-NEXT: v_add_i32_e32 v1, vcc, v2, v1
1958 ; GCN-IR-NEXT: v_sub_i32_e32 v0, vcc, 0x8000, v0
1959 ; GCN-IR-NEXT: v_subb_u32_e32 v1, vcc, 0, v1, vcc
1960 ; GCN-IR-NEXT: s_setpc_b64 s[30:31]
1978 ; GCN-IR-LABEL: v_test_srem_pow2_k_den_i64:
1979 ; GCN-IR: ; %bb.0: ; %_udiv-special-cases
1980 ; GCN-IR-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
1981 ; GCN-IR-NEXT: v_ashrrev_i32_e32 v2, 31, v1
1982 ; GCN-IR-NEXT: v_xor_b32_e32 v0, v0, v2
1983 ; GCN-IR-NEXT: v_sub_i32_e32 v0, vcc, v0, v2
1984 ; GCN-IR-NEXT: v_xor_b32_e32 v1, v1, v2
1985 ; GCN-IR-NEXT: v_ffbh_u32_e32 v3, v0
1986 ; GCN-IR-NEXT: v_subb_u32_e32 v1, vcc, v1, v2, vcc
1987 ; GCN-IR-NEXT: v_add_i32_e64 v3, s[4:5], 32, v3
1988 ; GCN-IR-NEXT: v_ffbh_u32_e32 v4, v1
1989 ; GCN-IR-NEXT: v_cmp_eq_u32_e64 s[4:5], 0, v1
1990 ; GCN-IR-NEXT: v_cndmask_b32_e64 v8, v4, v3, s[4:5]
1991 ; GCN-IR-NEXT: v_sub_i32_e64 v4, s[4:5], 48, v8
1992 ; GCN-IR-NEXT: v_subb_u32_e64 v5, s[4:5], 0, 0, s[4:5]
1993 ; GCN-IR-NEXT: v_cmp_eq_u64_e32 vcc, 0, v[0:1]
1994 ; GCN-IR-NEXT: v_cmp_lt_u64_e64 s[4:5], 63, v[4:5]
1995 ; GCN-IR-NEXT: v_mov_b32_e32 v3, v2
1996 ; GCN-IR-NEXT: s_or_b64 s[4:5], vcc, s[4:5]
1997 ; GCN-IR-NEXT: v_cmp_ne_u64_e32 vcc, 63, v[4:5]
1998 ; GCN-IR-NEXT: s_xor_b64 s[6:7], s[4:5], -1
1999 ; GCN-IR-NEXT: v_cndmask_b32_e64 v7, v1, 0, s[4:5]
2000 ; GCN-IR-NEXT: v_cndmask_b32_e64 v6, v0, 0, s[4:5]
2001 ; GCN-IR-NEXT: s_and_b64 s[4:5], s[6:7], vcc
2002 ; GCN-IR-NEXT: s_and_saveexec_b64 s[6:7], s[4:5]
2003 ; GCN-IR-NEXT: s_cbranch_execz BB13_6
2004 ; GCN-IR-NEXT: ; %bb.1: ; %udiv-bb1
2005 ; GCN-IR-NEXT: v_add_i32_e32 v9, vcc, 1, v4
2006 ; GCN-IR-NEXT: v_addc_u32_e32 v10, vcc, 0, v5, vcc
2007 ; GCN-IR-NEXT: v_cmp_ge_u64_e32 vcc, v[9:10], v[4:5]
2008 ; GCN-IR-NEXT: v_sub_i32_e64 v4, s[4:5], 63, v4
2009 ; GCN-IR-NEXT: v_mov_b32_e32 v6, 0
2010 ; GCN-IR-NEXT: v_lshl_b64 v[4:5], v[0:1], v4
2011 ; GCN-IR-NEXT: s_mov_b64 s[8:9], 0
2012 ; GCN-IR-NEXT: v_mov_b32_e32 v7, 0
2013 ; GCN-IR-NEXT: s_and_saveexec_b64 s[4:5], vcc
2014 ; GCN-IR-NEXT: s_xor_b64 s[10:11], exec, s[4:5]
2015 ; GCN-IR-NEXT: s_cbranch_execz BB13_5
2016 ; GCN-IR-NEXT: ; %bb.2: ; %udiv-preheader
2017 ; GCN-IR-NEXT: v_mov_b32_e32 v12, 0
2018 ; GCN-IR-NEXT: v_lshr_b64 v[10:11], v[0:1], v9
2019 ; GCN-IR-NEXT: v_add_i32_e32 v8, vcc, 0xffffffcf, v8
2020 ; GCN-IR-NEXT: v_addc_u32_e64 v9, s[4:5], 0, -1, vcc
2021 ; GCN-IR-NEXT: v_mov_b32_e32 v13, 0
2022 ; GCN-IR-NEXT: s_movk_i32 s12, 0x7fff
2023 ; GCN-IR-NEXT: BB13_3: ; %udiv-do-while
2024 ; GCN-IR-NEXT: ; =>This Inner Loop Header: Depth=1
2025 ; GCN-IR-NEXT: v_lshl_b64 v[10:11], v[10:11], 1
2026 ; GCN-IR-NEXT: v_lshrrev_b32_e32 v6, 31, v5
2027 ; GCN-IR-NEXT: v_or_b32_e32 v10, v10, v6
2028 ; GCN-IR-NEXT: v_lshl_b64 v[4:5], v[4:5], 1
2029 ; GCN-IR-NEXT: v_sub_i32_e32 v6, vcc, s12, v10
2030 ; GCN-IR-NEXT: v_subb_u32_e32 v6, vcc, 0, v11, vcc
2031 ; GCN-IR-NEXT: v_or_b32_e32 v4, v12, v4
2032 ; GCN-IR-NEXT: v_ashrrev_i32_e32 v12, 31, v6
2033 ; GCN-IR-NEXT: v_and_b32_e32 v14, 0x8000, v12
2034 ; GCN-IR-NEXT: v_and_b32_e32 v6, 1, v12
2035 ; GCN-IR-NEXT: v_add_i32_e32 v12, vcc, 1, v8
2036 ; GCN-IR-NEXT: v_or_b32_e32 v5, v13, v5
2037 ; GCN-IR-NEXT: v_addc_u32_e32 v13, vcc, 0, v9, vcc
2038 ; GCN-IR-NEXT: v_cmp_lt_u64_e32 vcc, v[12:13], v[8:9]
2039 ; GCN-IR-NEXT: v_mov_b32_e32 v8, v12
2040 ; GCN-IR-NEXT: v_mov_b32_e32 v7, 0
2041 ; GCN-IR-NEXT: v_mov_b32_e32 v9, v13
2042 ; GCN-IR-NEXT: v_mov_b32_e32 v13, v7
2043 ; GCN-IR-NEXT: v_mov_b32_e32 v15, 0
2044 ; GCN-IR-NEXT: v_sub_i32_e64 v10, s[4:5], v10, v14
2045 ; GCN-IR-NEXT: v_subb_u32_e64 v11, s[4:5], v11, v15, s[4:5]
2046 ; GCN-IR-NEXT: s_or_b64 s[8:9], vcc, s[8:9]
2047 ; GCN-IR-NEXT: v_mov_b32_e32 v12, v6
2048 ; GCN-IR-NEXT: s_andn2_b64 exec, exec, s[8:9]
2049 ; GCN-IR-NEXT: s_cbranch_execnz BB13_3
2050 ; GCN-IR-NEXT: ; %bb.4: ; %Flow
2051 ; GCN-IR-NEXT: s_or_b64 exec, exec, s[8:9]
2052 ; GCN-IR-NEXT: BB13_5: ; %Flow3
2053 ; GCN-IR-NEXT: s_or_b64 exec, exec, s[10:11]
2054 ; GCN-IR-NEXT: v_lshl_b64 v[4:5], v[4:5], 1
2055 ; GCN-IR-NEXT: v_or_b32_e32 v7, v7, v5
2056 ; GCN-IR-NEXT: v_or_b32_e32 v6, v6, v4
2057 ; GCN-IR-NEXT: BB13_6: ; %Flow4
2058 ; GCN-IR-NEXT: s_or_b64 exec, exec, s[6:7]
2059 ; GCN-IR-NEXT: v_lshl_b64 v[4:5], v[6:7], 15
2060 ; GCN-IR-NEXT: v_sub_i32_e32 v0, vcc, v0, v4
2061 ; GCN-IR-NEXT: v_subb_u32_e32 v1, vcc, v1, v5, vcc
2062 ; GCN-IR-NEXT: v_xor_b32_e32 v0, v0, v2
2063 ; GCN-IR-NEXT: v_xor_b32_e32 v1, v1, v3
2064 ; GCN-IR-NEXT: v_sub_i32_e32 v0, vcc, v0, v2
2065 ; GCN-IR-NEXT: v_subb_u32_e32 v1, vcc, v1, v3, vcc
2066 ; GCN-IR-NEXT: s_setpc_b64 s[30:31]
2099 ; GCN-IR-LABEL: s_test_srem24_k_num_i64:
2100 ; GCN-IR: ; %bb.0:
2101 ; GCN-IR-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x9
2102 ; GCN-IR-NEXT: s_mov_b32 s6, 0x41c00000
2103 ; GCN-IR-NEXT: s_waitcnt lgkmcnt(0)
2104 ; GCN-IR-NEXT: s_ashr_i64 s[4:5], s[2:3], 40
2105 ; GCN-IR-NEXT: v_cvt_f32_i32_e32 v0, s4
2106 ; GCN-IR-NEXT: s_ashr_i32 s5, s4, 30
2107 ; GCN-IR-NEXT: s_or_b32 s5, s5, 1
2108 ; GCN-IR-NEXT: v_mov_b32_e32 v3, s5
2109 ; GCN-IR-NEXT: v_rcp_iflag_f32_e32 v1, v0
2110 ; GCN-IR-NEXT: s_mov_b32 s3, 0xf000
2111 ; GCN-IR-NEXT: s_mov_b32 s2, -1
2112 ; GCN-IR-NEXT: v_mul_f32_e32 v1, s6, v1
2113 ; GCN-IR-NEXT: v_trunc_f32_e32 v1, v1
2114 ; GCN-IR-NEXT: v_mad_f32 v2, -v1, v0, s6
2115 ; GCN-IR-NEXT: v_cvt_i32_f32_e32 v1, v1
2116 ; GCN-IR-NEXT: v_cmp_ge_f32_e64 vcc, |v2|, |v0|
2117 ; GCN-IR-NEXT: v_cndmask_b32_e32 v0, 0, v3, vcc
2118 ; GCN-IR-NEXT: v_add_i32_e32 v0, vcc, v0, v1
2119 ; GCN-IR-NEXT: v_mul_lo_u32 v0, v0, s4
2120 ; GCN-IR-NEXT: v_sub_i32_e32 v0, vcc, 24, v0
2121 ; GCN-IR-NEXT: v_bfe_i32 v0, v0, 0, 24
2122 ; GCN-IR-NEXT: v_ashrrev_i32_e32 v1, 31, v0
2123 ; GCN-IR-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0
2124 ; GCN-IR-NEXT: s_endpgm
2161 ; GCN-IR-LABEL: s_test_srem24_k_den_i64:
2162 ; GCN-IR: ; %bb.0:
2163 ; GCN-IR-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x9
2164 ; GCN-IR-NEXT: s_mov_b32 s1, 0x46b6fe00
2165 ; GCN-IR-NEXT: s_mov_b32 s3, 0xf000
2166 ; GCN-IR-NEXT: s_mov_b32 s2, -1
2167 ; GCN-IR-NEXT: s_waitcnt lgkmcnt(0)
2168 ; GCN-IR-NEXT: s_ashr_i64 s[6:7], s[6:7], 40
2169 ; GCN-IR-NEXT: v_cvt_f32_i32_e32 v0, s6
2170 ; GCN-IR-NEXT: s_ashr_i32 s0, s6, 30
2171 ; GCN-IR-NEXT: s_or_b32 s0, s0, 1
2172 ; GCN-IR-NEXT: v_mov_b32_e32 v1, s0
2173 ; GCN-IR-NEXT: v_mul_f32_e32 v2, 0x38331158, v0
2174 ; GCN-IR-NEXT: v_trunc_f32_e32 v2, v2
2175 ; GCN-IR-NEXT: v_mad_f32 v0, -v2, s1, v0
2176 ; GCN-IR-NEXT: v_cvt_i32_f32_e32 v2, v2
2177 ; GCN-IR-NEXT: v_cmp_ge_f32_e64 vcc, |v0|, s1
2178 ; GCN-IR-NEXT: v_cndmask_b32_e32 v0, 0, v1, vcc
2179 ; GCN-IR-NEXT: s_movk_i32 s0, 0x5b7f
2180 ; GCN-IR-NEXT: v_add_i32_e32 v0, vcc, v0, v2
2181 ; GCN-IR-NEXT: v_mul_lo_u32 v0, v0, s0
2182 ; GCN-IR-NEXT: s_mov_b32 s0, s4
2183 ; GCN-IR-NEXT: s_mov_b32 s1, s5
2184 ; GCN-IR-NEXT: v_sub_i32_e32 v0, vcc, s6, v0
2185 ; GCN-IR-NEXT: v_bfe_i32 v0, v0, 0, 24
2186 ; GCN-IR-NEXT: v_ashrrev_i32_e32 v1, 31, v0
2187 ; GCN-IR-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0
2188 ; GCN-IR-NEXT: s_endpgm
2218 ; GCN-IR-LABEL: v_test_srem24_k_num_i64:
2219 ; GCN-IR: ; %bb.0:
2220 ; GCN-IR-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
2221 ; GCN-IR-NEXT: v_ashr_i64 v[0:1], v[0:1], 40
2222 ; GCN-IR-NEXT: s_mov_b32 s4, 0x41c00000
2223 ; GCN-IR-NEXT: v_cvt_f32_i32_e32 v1, v0
2224 ; GCN-IR-NEXT: v_ashrrev_i32_e32 v3, 30, v0
2225 ; GCN-IR-NEXT: v_or_b32_e32 v3, 1, v3
2226 ; GCN-IR-NEXT: v_rcp_iflag_f32_e32 v2, v1
2227 ; GCN-IR-NEXT: v_mul_f32_e32 v2, s4, v2
2228 ; GCN-IR-NEXT: v_trunc_f32_e32 v2, v2
2229 ; GCN-IR-NEXT: v_mad_f32 v4, -v2, v1, s4
2230 ; GCN-IR-NEXT: v_cvt_i32_f32_e32 v2, v2
2231 ; GCN-IR-NEXT: v_cmp_ge_f32_e64 vcc, |v4|, |v1|
2232 ; GCN-IR-NEXT: v_cndmask_b32_e32 v1, 0, v3, vcc
2233 ; GCN-IR-NEXT: v_add_i32_e32 v1, vcc, v2, v1
2234 ; GCN-IR-NEXT: v_mul_lo_u32 v0, v1, v0
2235 ; GCN-IR-NEXT: v_sub_i32_e32 v0, vcc, 24, v0
2236 ; GCN-IR-NEXT: v_bfe_i32 v0, v0, 0, 24
2237 ; GCN-IR-NEXT: v_ashrrev_i32_e32 v1, 31, v0
2238 ; GCN-IR-NEXT: s_setpc_b64 s[30:31]
2267 ; GCN-IR-LABEL: v_test_srem24_pow2_k_num_i64:
2268 ; GCN-IR: ; %bb.0:
2269 ; GCN-IR-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
2270 ; GCN-IR-NEXT: v_ashr_i64 v[0:1], v[0:1], 40
2271 ; GCN-IR-NEXT: s_mov_b32 s4, 0x47000000
2272 ; GCN-IR-NEXT: v_cvt_f32_i32_e32 v1, v0
2273 ; GCN-IR-NEXT: v_ashrrev_i32_e32 v3, 30, v0
2274 ; GCN-IR-NEXT: v_or_b32_e32 v3, 1, v3
2275 ; GCN-IR-NEXT: v_rcp_iflag_f32_e32 v2, v1
2276 ; GCN-IR-NEXT: v_mul_f32_e32 v2, s4, v2
2277 ; GCN-IR-NEXT: v_trunc_f32_e32 v2, v2
2278 ; GCN-IR-NEXT: v_mad_f32 v4, -v2, v1, s4
2279 ; GCN-IR-NEXT: v_cvt_i32_f32_e32 v2, v2
2280 ; GCN-IR-NEXT: v_cmp_ge_f32_e64 vcc, |v4|, |v1|
2281 ; GCN-IR-NEXT: v_cndmask_b32_e32 v1, 0, v3, vcc
2282 ; GCN-IR-NEXT: v_add_i32_e32 v1, vcc, v2, v1
2283 ; GCN-IR-NEXT: v_mul_lo_u32 v0, v1, v0
2284 ; GCN-IR-NEXT: v_sub_i32_e32 v0, vcc, 0x8000, v0
2285 ; GCN-IR-NEXT: v_bfe_i32 v0, v0, 0, 24
2286 ; GCN-IR-NEXT: v_ashrrev_i32_e32 v1, 31, v0
2287 ; GCN-IR-NEXT: s_setpc_b64 s[30:31]
2306 ; GCN-IR-LABEL: v_test_srem24_pow2_k_den_i64:
2307 ; GCN-IR: ; %bb.0:
2308 ; GCN-IR-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
2309 ; GCN-IR-NEXT: v_ashr_i64 v[0:1], v[0:1], 40
2310 ; GCN-IR-NEXT: s_mov_b32 s4, 0x47000000
2311 ; GCN-IR-NEXT: v_cvt_f32_i32_e32 v1, v0
2312 ; GCN-IR-NEXT: v_ashrrev_i32_e32 v2, 30, v0
2313 ; GCN-IR-NEXT: v_or_b32_e32 v2, 1, v2
2314 ; GCN-IR-NEXT: v_mul_f32_e32 v3, 0x38000000, v1
2315 ; GCN-IR-NEXT: v_trunc_f32_e32 v3, v3
2316 ; GCN-IR-NEXT: v_mad_f32 v1, -v3, s4, v1
2317 ; GCN-IR-NEXT: v_cvt_i32_f32_e32 v3, v3
2318 ; GCN-IR-NEXT: v_cmp_ge_f32_e64 vcc, |v1|, s4
2319 ; GCN-IR-NEXT: v_cndmask_b32_e32 v1, 0, v2, vcc
2320 ; GCN-IR-NEXT: v_add_i32_e32 v1, vcc, v3, v1
2321 ; GCN-IR-NEXT: v_lshlrev_b32_e32 v1, 15, v1
2322 ; GCN-IR-NEXT: v_sub_i32_e32 v0, vcc, v0, v1
2323 ; GCN-IR-NEXT: v_bfe_i32 v0, v0, 0, 24
2324 ; GCN-IR-NEXT: v_ashrrev_i32_e32 v1, 31, v0
2325 ; GCN-IR-NEXT: s_setpc_b64 s[30:31]