Lines Matching refs:GFX1032

1 …efrontsize32,-wavefrontsize64 -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,GFX1032 %s
3 …tsize64 -amdgpu-early-ifcvt=1 -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,GFX1032 %s
5 …cn -mcpu=gfx1010 -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,GFX1032,GFX10DEFWAVE %s
8 ; GFX1032: v_cmp_lt_i32_e32 vcc_lo, 0, v{{[0-9]+}}
9 ; GFX1032: v_cndmask_b32_e64 v{{[0-9]+}}, 2, 1, vcc_lo
23 ; GFX1032: v_cmp_nge_f32_e32 vcc_lo, 0, v{{[0-9]+}}
24 ; GFX1032: v_cndmask_b32_e64 v{{[0-9]+}}, 2.0, 1.0, vcc_lo
38 ; GFX1032: v_cmpx_le_f32_e32 0, v{{[0-9]+}}
47 ; GFX1032: v_cmp_le_f16_sdwa [[SC:vcc_lo|s[0-9]+]], {{[vs][0-9]+}}, v{{[0-9]+}} src0_sel:WORD_1 src…
48 ; GFX1032: v_cndmask_b32_e32 v{{[0-9]+}}, 0x3c003c00, v{{[0-9]+}}, [[SC]]
63 ; GFX1032: v_cmp_class_f32_e64 [[C:vcc_lo|s[0-9:]+]], s{{[0-9]+}}, 0x204
64 ; GFX1032: v_cndmask_b32_e64 v{{[0-9]+}}, 0, 1, [[C]]
76 ; GFX1032: v_cmp_neq_f16_e64 [[C:vcc_lo|s\[[0-9:]+\]]], 0x7c00, s{{[0-9]+}}
77 ; GFX1032: v_cndmask_b32_e32 v{{[0-9]+}}, 0x3c00, v{{[0-9]+}}, [[C]]
89 ; GFX1032: v_cmp_nge_f32_e32 vcc_lo, 0, v{{[0-9]+}}
90 ; GFX1032: v_cmp_nle_f32_e64 [[C2:s[0-9]+]], 1.0, v{{[0-9]+}}
91 ; GFX1032: s_and_b32 [[AND:s[0-9]+]], vcc_lo, [[C2]]
92 ; GFX1032: v_cndmask_b32_e64 v{{[0-9]+}}, 2.0, 1.0, [[AND]]
110 ; GFX1032: v_cmp_lt_i32_e32 vcc_lo, 0, v{{[0-9]+}}
111 ; GFX1032: v_cmp_gt_i32_e64 [[C2:s[0-9]+]], 1, v{{[0-9]+}}
112 ; GFX1032: s_xor_b32 [[AND:s[0-9]+]], vcc_lo, [[C2]]
113 ; GFX1032: v_cndmask_b32_e64 v{{[0-9]+}}, 2, 1, [[AND]]
131 ; GFX1032: v_cmp_lt_u32_e32 vcc_lo, 3, v{{[0-9]+}}
132 ; GFX1032: v_cmp_gt_u32_e64 [[C2:s[0-9]+]], 2, v{{[0-9]+}}
133 ; GFX1032: s_or_b32 [[AND:s[0-9]+]], vcc_lo, [[C2]]
134 ; GFX1032: v_cndmask_b32_e64 v{{[0-9]+}}, 2, 1, [[AND]]
152 ; GFX1032: s_and_saveexec_b32 s{{[0-9]+}}, vcc_lo
169 ; GFX1032: s_or_b32 s{{[0-9]+}}, vcc_lo, s{{[0-9]+}}
170 ; GFX1032: s_andn2_b32 exec_lo, exec_lo, s{{[0-9]+}}
175 ; GFX1032: s_and_saveexec_b32 s{{[0-9]+}}, vcc_lo
180 ; GFX1032: s_xor_b32 s{{[0-9]+}}, exec_lo, s{{[0-9]+}}
184 ; GFX1032: s_or_b32 exec_lo, exec_lo, s{{[0-9]+}}
185 ; GFX1032: s_and_saveexec_b32 s{{[0-9]+}}, s{{[0-9]+}}
228 ; GFX1032: s_and_saveexec_b32 s{{[0-9]+}}, vcc_lo
234 ; GFX1032: s_or_b32 [[MASK0:s[0-9]+]], [[MASK0]], vcc_lo
237 ; GFX1032: s_andn2_b32 [[MASK1:s[0-9]+]], [[MASK1]], exec_lo
239 ; GFX1032: s_and_b32 [[MASK0]], [[MASK0]], exec_lo
241 ; GFX1032: s_or_b32 [[MASK1]], [[MASK1]], [[MASK0]]
244 ; GFX1032: s_and_b32 [[TMP0:s[0-9]+]], exec_lo, [[MASK1]]
246 ; GFX1032: s_or_b32  [[ACC:s[0-9]+]], [[TMP0]], [[ACC]]
248 ; GFX1032: s_andn2_b32 exec_lo, exec_lo, [[ACC]]
253 ; GFX1032: s_or_b32 [[MASK1]], [[MASK1]], exec_lo
286 ; GFX1032: v_add_co_u32_e64 v{{[0-9]+}}, vcc_lo, v{{[0-9]+}}, s{{[0-9]+}}
287 ; GFX1032: v_add_co_ci_u32_e32 v{{[0-9]+}}, vcc_lo, s{{[0-9]+}}, v{{[0-9]+}}, vcc_lo
301 ; GFX1032: v_sub_co_u32_e64 v{{[0-9]+}}, [[A0:s[0-9]+|vcc_lo]], v{{[0-9]+}}, s{{[0-9]+}}{{$}}
302 ; GFX1032: v_subrev_co_ci_u32_e32 v{{[0-9]+}}, vcc_lo, {{[vs][0-9]+}}, {{[vs][0-9]+}}, [[A0]]{{$}}
316 ; GFX1032: v_sub_co_u32_e64 v{{[0-9]+}}, [[A0:s[0-9]+|vcc_lo]], s{{[0-9]+}}, v{{[0-9]+}}{{$}}
317 ; GFX1032: v_sub_co_ci_u32_e32 v{{[0-9]+}}, vcc_lo, {{[vs][0-9]+}}, v{{[0-9]+}}, [[A0]]{{$}}
331 ; GFX1032: v_add_co_u32_e64 v{{[0-9]+}}, [[SDST:s[0-9]+]], v{{[0-9]+}}, v{{[0-9]+}}
332 ; GFX1032: v_add_co_ci_u32_e32 v{{[0-9]+}}, vcc_lo, 0, v{{[0-9]+}}, vcc_lo
333 ; GFX1032: v_add_co_ci_u32_e64 v{{[0-9]+}}, vcc_lo, v{{[0-9]+}}, v{{[0-9]+}}, [[SDST]]
334 ; GFX1032: v_add_co_u32_e64 v{{[0-9]+}}, vcc_lo, v{{[0-9]+}}, v{{[0-9]+}}
335 ; GFX1032: v_add_co_u32_e64 v{{[0-9]+}}, vcc_lo, v{{[0-9]+}}, v{{[0-9]+}}
336 ; GFX1032: v_add_co_u32_e64 v{{[0-9]+}}, vcc_lo, v{{[0-9]+}}, v{{[0-9]+}}
337 ; GFX1032: v_add_co_ci_u32_e32 v{{[0-9]+}}, vcc_lo, 0, v{{[0-9]+}}, vcc_lo
338 ; GFX1032: v_sub_co_u32_e64 v{{[0-9]+}}, vcc_lo, s{{[0-9]+}}, v{{[0-9]+}}
339 ; GFX1032: v_subrev_co_ci_u32_e64 v{{[0-9]+}}, s{{[0-9]+}}, {{[vs][0-9]+}}, v{{[0-9]+}}, vcc_lo
340 ; GFX1032: v_sub_co_ci_u32_e32 v{{[0-9]+}}, vcc_lo, {{[vs][0-9]+}}, v{{[0-9]+}}, vcc_lo
363 ; GFX1032: v_div_scale_f32 v{{[0-9]+}}, s{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}}
380 ; GFX1032: v_div_scale_f64 v[{{[0-9:]+}}], s{{[0-9]+}}, v[{{[0-9:]+}}], v[{{[0-9:]+}}], v[{{[0-9:]+…
397 ; GFX1032: v_mad_i64_i32 v[{{[0-9:]+}}], s{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}}, v[{{[0-9:]+}}]
408 ; GFX1032: v_mad_u64_u32 v[{{[0-9:]+}}], s{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}}, v[{{[0-9:]+}}]
419 ; GFX1032: v_cmp_eq_u32_e64 vcc_lo,
429 ; GFX1032: v_cmp_eq_u32_e64 vcc_lo,
439 ; GFX1032: s_mov_b32 [[VCC:vcc_lo]], 0{{$}}
441 ; GFX1032: s_and_saveexec_b32 [[SAVE:s[0-9]+]], s{{[0-9]+}}{{$}}
448 ; GFX1032: s_or_b32 exec_lo, exec_lo, [[SAVE]]
479 ; GFX1032: v_div_scale_f32 v{{[0-9]+}}, s{{[0-9]+}}, s{{[0-9]+}}, s{{[0-9]+}}, s{{[0-9]+}}
482 ; GFX1032: v_div_scale_f32 v{{[0-9]+}}, vcc_lo, s{{[0-9]+}}, s{{[0-9]+}}, s{{[0-9]+}}
495 ; GFX1032:  v_cmp_nlt_f16_e32 vcc_lo,
496 ; GFX1032:  s_and_b32 vcc_lo, exec_lo, vcc_lo
535 ; GFX1032-DAG: v_cmp_nlt_f32_e64 s{{[0-9]+}}, s{{[0-9]+}}, 1.0
536 ; GFX1032-DAG: v_cmp_ngt_f32_e64 s{{[0-9]+}}, s{{[0-9]+}}, 0
537 ; GFX1032: v_cmp_nlt_f32_e64 s{{[0-9]+}}, s{{[0-9]+}}, 1.0
538 ; GFX1032: s_or_b32 [[OR1:s[0-9]+]], s{{[0-9]+}}, s{{[0-9]+}}
539 ; GFX1032: s_or_b32 [[OR2:s[0-9]+]], [[OR1]], s{{[0-9]+}}
540 ; GFX1032: s_and_b32 vcc_lo, exec_lo, [[OR2]]
569 ; GFX1032: s_xor_b32 s{{[0-9]+}}, s{{[0-9]+}}, -1
570 ; GFX1032: s_or_b32 s{{[0-9]+}}, s{{[0-9]+}}, s{{[0-9]+}}
601 ; GFX1032: v_cmp_eq_u32_e32 vcc_lo, 1, v{{[0-9]+}}
602 ; GFX1032: v_cndmask_b32_e64 v{{[0-9]+}}, 0, 1, vcc_lo
603 ; GFX1032: v_cmp_ne_u32_e32 vcc_lo, 2, v{{[0-9]+}}
604 ; GFX1032: v_cndmask_b32_e32 v{{[0-9]+}}, 2, v{{[0-9]+}}, vcc_lo
605 ; GFX1032: v_cmp_ne_u32_e32 vcc_lo, 3, v{{[0-9]+}}
606 ; GFX1032: v_cndmask_b32_e32 v{{[0-9]+}}, 3, v{{[0-9]+}}, vcc_lo
623 ; GFX1032: s_not_b32 exec_lo, exec_lo
624 ; GFX1032: v_mov_b32_e32 {{v[0-9]+}}, 42
625 ; GFX1032: s_not_b32 exec_lo, exec_lo
636 ; GFX1032: s_not_b32 exec_lo, exec_lo
637 ; GFX1032: v_mov_b32_e32 {{v[0-9]+}}, 0
638 ; GFX1032: v_mov_b32_e32 {{v[0-9]+}}, 0
639 ; GFX1032: s_not_b32 exec_lo, exec_lo
651 ; GFX1032: s_mov_b32 exec_lo, 0
659 ; GFX1032: s_or_b32 [[OR:s[0-9]+]],
660 ; GFX1032: s_and_b32 exec_lo, exec_lo, [[OR]]
672 ; GFX1032: v_cmp_lt_f32_e32 vcc_lo,
696 ; GFX1032: s_or_saveexec_b32 [[SAVE:s[0-9]+]], -1
697 ; GFX1032: s_mov_b32 exec_lo, [[SAVE]]
708 ; GFX1032: v_cmp_gt_u32_e32 vcc_lo, 32, v{{[0-9]+}}
709 ; GFX1032: s_and_saveexec_b32 [[SAVE1:s[0-9]+]], vcc_lo
710 ; GFX1032: s_or_saveexec_b32 [[SAVE2:s[0-9]+]], -1
711 ; GFX1032: s_mov_b32 exec_lo, [[SAVE2]]
712 ; GFX1032: s_or_b32 exec_lo, exec_lo, [[SAVE1]]
739 ; GFX1032: s_mov_b32 [[ORIG:s[0-9]+]], exec_lo
740 ; GFX1032: s_wqm_b32 exec_lo, exec_lo
741 ; GFX1032: s_and_b32 exec_lo, exec_lo, [[ORIG]]
758 ; GFX1032: s_wqm_b32 exec_lo, exec_lo
759 ; GFX1032: s_and_b32 exec_lo, exec_lo, s{{[0-9+]}}
774 ; GFX1032-DAG: v_mov_b32_e32 v[[V_HI:[0-9]+]], 0{{$}}
775 ; GFX1032-DAG: v_cmp_eq_f32_e64 s[[C_LO:[0-9]+]], {{s[0-9]+}}, |{{[vs][0-9]+}}|
776 ; GFX1032-DAG: v_mov_b32_e32 v[[V_LO:[0-9]+]], s[[C_LO]]
789 ; GFX1032-DAG: v_mov_b32_e32 v[[V_HI:[0-9]+]], 0{{$}}
790 ; GFX1032-DAG: v_cmp_eq_u32_e64 [[C_LO:vcc_lo|s[0-9]+]], 0x64, {{s[0-9]+}}
791 ; GFX1032-DAG: v_mov_b32_e32 v[[V_LO:[0-9]+]], [[C_LO]]
803 ; GFX1032-DAG: v_cmp_eq_f32_e64 s[[C_LO:[0-9]+]], {{s[0-9]+}}, |{{[vs][0-9]+}}|
804 ; GFX1032-DAG: v_mov_b32_e32 v[[V_LO:[0-9]+]], s[[C_LO]]
816 ; GFX1032-DAG: v_cmp_eq_u32_e64 s[[C_LO:[0-9]+]], 0x64, {{s[0-9]+}}
817 ; GFX1032-DAG: v_mov_b32_e32 v[[V_LO:[0-9]+]], s[[C_LO]]{{$}}
828 ; GFX1032: v_cmp_neq_f32_e32 vcc_lo, 0
829 ; GFX1032: s_wqm_b32 [[WQM:s[0-9]+]], vcc_lo
830 ; GFX1032: s_and_b32 exec_lo, exec_lo, [[WQM]]
842 ; GFX1032: s_mov_b32 vcc_lo, exec_lo
859 ; GFX1032: s_mov_b32 [[C:s[0-9]+]], exec_lo
870 ; GFX1032: v_cmp_neq_f64_e64 [[C:s[0-9]+]], s[{{[0-9:]+}}], 1.0
871 ; GFX1032: s_and_b32 vcc_lo, exec_lo, [[C]]
931 ; GFX1032: v_cmp_eq_u32_e32 vcc_lo, 0, v
962 ; GFX1032: v_cmp_eq_f32_e32 vcc_lo, 0, v
994 ; GFX1032: v_cmp_eq_u32_e32 vcc_lo, 0, v
1024 ; GFX1032: v_cmp_eq_f32_e32 vcc_lo, 0, v
1063 ; GFX1032-NEXT: s_or_saveexec_b32 [[COPY_EXEC0:s[0-9]]], -1{{$}}
1067 ; GFX1032-NEXT: s_mov_b32 exec_lo, [[COPY_EXEC0]]
1072 ; GFX1032: s_add_u32 s32, s32, 0x200
1083 ; GFX1032: s_sub_u32 s32, s32, 0x200
1086 ; GFX1032: s_or_saveexec_b32 [[COPY_EXEC1:s[0-9]]], -1{{$}}
1090 ; GFX1032-NEXT: s_mov_b32 exec_lo, [[COPY_EXEC1]]