Lines Matching refs:umull

4 ; Armv6 generates a umull that must write to two distinct destination regs.
25   ; CHECK: umull [[REGISTER:lr|r[0-9]+]],
28   ; CHECK: umull [[REGISTER:lr|r[0-9]+]],
39   ; CHECK: umull [[REGISTER:lr|r[0-9]+]],
42   ; CHECK: umull [[REGISTER:lr|r[0-9]+]],
53   ; CHECK: umull [[REGISTER:lr|r[0-9]+]],
56   ; CHECK: umull [[REGISTER:lr|r[0-9]+]],
67   ; CHECK: umull [[REGISTER:lr|r[0-9]+]],
70   ; CHECK: umull [[REGISTER:lr|r[0-9]+]],
78   ; CHECK: umull [[REGISTER:lr|r[0-9]+]],
81   ; CHECK: umull [[REGISTER:lr|r[0-9]+]],
92   ; CHECK: umull [[REGISTER:lr|r[0-9]+]],
95   ; CHECK: umull [[REGISTER:lr|r[0-9]+]],