Lines Matching refs:bfloat
3 ; FIXME: Remove fullfp16 once bfloat arguments and returns lowering stops
9 define arm_aapcs_vfpcc <4 x bfloat> @test_vcreate_bf16(i64 %a) {
15 %0 = bitcast i64 %a to <4 x bfloat>
16 ret <4 x bfloat> %0
19 define arm_aapcs_vfpcc <4 x bfloat> @test_vdup_n_bf16(bfloat %v) {
26 %vecinit.i = insertelement <4 x bfloat> undef, bfloat %v, i32 0
27 %vecinit3.i = shufflevector <4 x bfloat> %vecinit.i, <4 x bfloat> undef, <4 x i32> zeroinitializer
28 ret <4 x bfloat> %vecinit3.i
31 define arm_aapcs_vfpcc <8 x bfloat> @test_vdupq_n_bf16(bfloat %v) {
38 %vecinit.i = insertelement <8 x bfloat> undef, bfloat %v, i32 0
39 %vecinit7.i = shufflevector <8 x bfloat> %vecinit.i, <8 x bfloat> undef, <8 x i32> zeroinitializer
40 ret <8 x bfloat> %vecinit7.i
43 define arm_aapcs_vfpcc <4 x bfloat> @test_vdup_lane_bf16(<4 x bfloat> %v) {
49 %lane = shufflevector <4 x bfloat> %v, <4 x bfloat> undef, <4 x i32> <i32 1, i32 1, i32 1, i32 1>
50 ret <4 x bfloat> %lane
53 define arm_aapcs_vfpcc <8 x bfloat> @test_vdupq_lane_bf16(<4 x bfloat> %v) {
60 …%lane = shufflevector <4 x bfloat> %v, <4 x bfloat> undef, <8 x i32> <i32 1, i32 1, i32 1, i32 1, …
61 ret <8 x bfloat> %lane
64 define arm_aapcs_vfpcc <4 x bfloat> @test_vdup_laneq_bf16(<8 x bfloat> %v) {
70 %lane = shufflevector <8 x bfloat> %v, <8 x bfloat> undef, <4 x i32> <i32 7, i32 7, i32 7, i32 7>
71 ret <4 x bfloat> %lane
74 define arm_aapcs_vfpcc <8 x bfloat> @test_vdupq_laneq_bf16(<8 x bfloat> %v) {
80 …%lane = shufflevector <8 x bfloat> %v, <8 x bfloat> undef, <8 x i32> <i32 7, i32 7, i32 7, i32 7, …
81 ret <8 x bfloat> %lane
84 define arm_aapcs_vfpcc <8 x bfloat> @test_vcombine_bf16(<4 x bfloat> %low, <4 x bfloat> %high) {
92 …%shuffle.i = shufflevector <4 x bfloat> %high, <4 x bfloat> %low, <8 x i32> <i32 0, i32 1, i32 2, …
93 ret <8 x bfloat> %shuffle.i
96 define arm_aapcs_vfpcc <4 x bfloat> @test_vget_high_bf16(<8 x bfloat> %a) {
102 …%shuffle.i = shufflevector <8 x bfloat> %a, <8 x bfloat> undef, <4 x i32> <i32 4, i32 5, i32 6, i3…
103 ret <4 x bfloat> %shuffle.i
106 define arm_aapcs_vfpcc <4 x bfloat> @test_vget_low_bf16(<8 x bfloat> %a) {
112 …%shuffle.i = shufflevector <8 x bfloat> %a, <8 x bfloat> undef, <4 x i32> <i32 0, i32 1, i32 2, i3…
113 ret <4 x bfloat> %shuffle.i
116 define arm_aapcs_vfpcc bfloat @test_vgetq_lane_bf16_even(<8 x bfloat> %v) {
122 %0 = extractelement <8 x bfloat> %v, i32 6
123 ret bfloat %0
126 define arm_aapcs_vfpcc bfloat @test_vgetq_lane_bf16_odd(<8 x bfloat> %v) {
132 %0 = extractelement <8 x bfloat> %v, i32 7
133 ret bfloat %0
136 define arm_aapcs_vfpcc bfloat @test_vget_lane_bf16_even(<4 x bfloat> %v) {
142 %0 = extractelement <4 x bfloat> %v, i32 2
143 ret bfloat %0
146 define arm_aapcs_vfpcc bfloat @test_vget_lane_bf16_odd(<4 x bfloat> %v) {
152 %0 = extractelement <4 x bfloat> %v, i32 1
153 ret bfloat %0
156 define arm_aapcs_vfpcc <4 x bfloat> @test_vset_lane_bf16(bfloat %a, <4 x bfloat> %v) {
164 %0 = insertelement <4 x bfloat> %v, bfloat %a, i32 1
165 ret <4 x bfloat> %0
168 define arm_aapcs_vfpcc <8 x bfloat> @test_vsetq_lane_bf16(bfloat %a, <8 x bfloat> %v) {
176 %0 = insertelement <8 x bfloat> %v, bfloat %a, i32 7
177 ret <8 x bfloat> %0